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armjit: Optimize out a few immediate logic cases.

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This commit is contained in:
Unknown W. Brackets 2013-11-08 09:09:09 -08:00
parent 385f9a457e
commit 02dd250354
2 changed files with 31 additions and 1 deletions
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30
Core/MIPS/ARM/ArmCompALU.cpp
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@ -100,6 +100,10 @@ namespace MIPSComp
case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
{
if (gpr.IsImm(rs)) {
gpr.SetImm(rt, (s32)gpr.GetImm(rs) < simm ? 1 : 0);
break;
}
gpr.MapDirtyIn(rt, rs);
CMPI2R(gpr.R(rs), simm, R0);
SetCC(CC_LT);
@ -112,6 +116,10 @@ namespace MIPSComp
case 11: // R(rt) = R(rs) < uimm; break; //sltiu
{
if (gpr.IsImm(rs)) {
gpr.SetImm(rt, gpr.GetImm(rs) < suimm ? 1 : 0);
break;
}
gpr.MapDirtyIn(rt, rs);
CMPI2R(gpr.R(rs), suimm, R0);
SetCC(CC_LO);
@ -145,10 +153,32 @@ namespace MIPSComp
switch (op & 63)
{
case 22: //clz
if (gpr.IsImm(rs)) {
u32 value = gpr.GetImm(rs);
int x = 31;
int count = 0;
while (!(value & (1 << x)) && x >= 0) {
count++;
x--;
}
gpr.SetImm(rd, count);
break;
}
gpr.MapDirtyIn(rd, rs);
CLZ(gpr.R(rd), gpr.R(rs));
break;
case 23: //clo
if (gpr.IsImm(rs)) {
u32 value = gpr.GetImm(rs);
int x = 31;
int count = 0;
while ((value & (1 << x)) && x >= 0) {
count++;
x--;
}
gpr.SetImm(rd, count);
break;
}
gpr.MapDirtyIn(rd, rs);
MVN(R0, gpr.R(rs));
CLZ(gpr.R(rd), R0);

2
Core/MIPS/x86/CompALU.cpp
View File

@ -96,7 +96,7 @@ namespace MIPSComp
break;
case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
// There's a mips compiler out there asking it already knows the answer to...
// There's a mips compiler out there asking questions it already knows the answer to...
if (gpr.IsImmediate(rs))
{
gpr.SetImmediate32(rt, (s32)gpr.GetImmediate32(rs) < simm);