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x86jit: Fix andLink cases of imm blezl, etc.

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Unknown W. Brackets 2014-10-24 08:57:56 -07:00
parent e2926da4f3
commit 100afc07a2
1 changed files with 1 additions and 1 deletions
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2
Core/MIPS/x86/CompBranch.cpp
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@ -421,7 +421,7 @@ void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool li
CONDITIONAL_NICE_DELAYSLOT;
if (immBranch)
CompBranchExit(immBranchTaken, targetAddr, js.compilerPC + 8, delaySlotIsNice, likely, false);
CompBranchExit(immBranchTaken, targetAddr, js.compilerPC + 8, delaySlotIsNice, likely, andLink);
else
{
if (!likely && delaySlotIsNice)