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Merge pull request #8740 from unknownbrackets/ir-vfpu
More VFPU comments, implement vmscl
This commit is contained in:
Henrik Rydgård
commit
168573e711
@ -380,7 +380,7 @@ namespace MIPSComp {
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DISABLE;
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}
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// Matrix init
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// Matrix init (no prefixes)
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// d[N,M] = CONST[N,M]
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// Not really about trying here, it will work if enabled.
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@ -856,10 +856,21 @@ namespace MIPSComp {
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}
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void IRFrontend::Comp_Vh2f(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// Vector expand half to float
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// d[N*2] = float(lowerhalf(s[N])), d[N*2+1] = float(upperhalf(s[N]))
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DISABLE;
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}
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void IRFrontend::Comp_Vf2i(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// Vector float to integer
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// d[N] = int(S[N] * mult)
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// Note: saturates on overflow.
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DISABLE;
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}
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@ -911,7 +922,7 @@ namespace MIPSComp {
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void IRFrontend::Comp_Vmfvc(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// Vector Move from vector control reg
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// Vector Move from vector control reg (no prefixes)
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// S[0] = VFPU_CTRL[i]
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int vs = _VS;
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@ -931,7 +942,7 @@ namespace MIPSComp {
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void IRFrontend::Comp_Vmtvc(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// Vector Move to vector control reg
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// Vector Move to vector control reg (no prefixes)
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// VFPU_CTRL[i] = S[0]
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int vs = _VS;
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@ -951,7 +962,7 @@ namespace MIPSComp {
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void IRFrontend::Comp_Vmmov(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// Matrix move
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// Matrix move (no prefixes)
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// D[N,M] = S[N,M]
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int vs = _VS;
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@ -1009,9 +1020,41 @@ namespace MIPSComp {
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}
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void IRFrontend::Comp_Vmscl(MIPSOpcode op) {
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DISABLE;
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CONDITIONAL_DISABLE;
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// TODO: Tricky, can transpose
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// Matrix scale, matrix by scalar (no prefixes)
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// d[N,M] = s[N,M] * t[0]
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int vs = _VS;
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int vd = _VD;
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int vt = _VT;
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MatrixSize sz = GetMtxSize(op);
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if (sz != M_4x4) {
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DISABLE;
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}
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if (GetMtx(vt) == GetMtx(vd)) {
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DISABLE;
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}
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int n = GetMatrixSide(sz);
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// The entire matrix is scaled equally, so transpose doesn't matter. Let's normalize.
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if (IsMatrixTransposed(vs) && IsMatrixTransposed(vd)) {
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vs = TransposeMatrixReg(vs);
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vd = TransposeMatrixReg(vd);
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}
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if (IsMatrixTransposed(vs) || IsMatrixTransposed(vd)) {
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DISABLE;
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}
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u8 sregs[16], dregs[16], tregs[1];
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GetMatrixRegs(sregs, sz, vs);
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GetMatrixRegs(dregs, sz, vd);
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GetVectorRegs(tregs, V_Single, vt);
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for (int i = 0; i < n; ++i) {
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ir.Write(IROp::Vec4Scale, dregs[i * 4], sregs[i * 4], tregs[0]);
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}
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}
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void IRFrontend::Comp_VScl(MIPSOpcode op) {
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@ -1090,9 +1133,9 @@ namespace MIPSComp {
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// Many more instructions to interpret.
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void IRFrontend::Comp_Vmmul(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix()) {
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DISABLE;
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}
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// Matrix multiply (no prefixes)
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// D[0 .. N,0 .. M] = S[0 .. N, 0 .. M] * T[0 .. N,0 .. M]
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MatrixSize sz = GetMtxSize(op);
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int n = GetMatrixSide(sz);
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@ -1173,11 +1216,8 @@ namespace MIPSComp {
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void IRFrontend::Comp_Vtfm(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix()) {
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DISABLE;
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}
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// Vertex transform, vector by matrix
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// Vertex transform, vector by matrix (no prefixes)
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// d[N] = s[N*m .. N*m + n-1] dot t[0 .. n-1]
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// Homogenous means t[n-1] is treated as 1.
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@ -1213,10 +1253,10 @@ namespace MIPSComp {
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ir.Write(IROp::Vec4Scale, s0, sregs[0], tregs[0]);
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for (int i = 1; i < 4; i++) {
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if (!homogenous || (i != n - 1)) {
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ir.Write(IROp::Vec4Scale, s1, sregs[i * 4], tregs[i]);
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ir.Write(IROp::Vec4Scale, s1, sregs[i], tregs[i]);
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ir.Write(IROp::Vec4Add, s0, s0, s1);
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} else {
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ir.Write(IROp::Vec4Add, s0, s0, sregs[i * 4]);
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ir.Write(IROp::Vec4Add, s0, s0, sregs[i]);
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}
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}
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if (IsConsecutive4(dregs)) {
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@ -1277,10 +1317,29 @@ namespace MIPSComp {
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}
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void IRFrontend::Comp_VCrs(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix()) {
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DISABLE;
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}
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// Vector cross (half a cross product, n = 3)
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// d[0] = s[y]*t[z], d[1] = s[z]*t[x], d[2] = s[x]*t[y]
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// To do a full cross product: vcrs tmp1, s, t; vcrs tmp2 t, s; vsub d, tmp1, tmp2;
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// (or just use vcrsp.)
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DISABLE;
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}
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void IRFrontend::Comp_VDet(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix()) {
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DISABLE;
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}
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// Vector determinant
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// d[0] = s[0]*t[1] - s[1]*t[0]
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// Note: this operates on two vectors, not a 2x2 matrix.
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DISABLE;
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}
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@ -1294,10 +1353,16 @@ namespace MIPSComp {
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void IRFrontend::Comp_VCrossQuat(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// TODO: Does this instruction even look at prefixes at all?
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if (js.HasUnknownPrefix())
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DISABLE;
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// Vector cross product (n = 3)
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// d[0 .. 2] = s[0 .. 2] X t[0 .. 2]
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// Vector quaternion product (n = 4)
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// d[0 .. 2] = t[0 .. 2] X s[0 .. 2] + s[3] * t[0 .. 2] + t[3] * s[0 .. 2]
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// d[3] = s[3]*t[3] - s[0 .. 2] dot t[0 .. 3]
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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@ -1348,6 +1413,9 @@ namespace MIPSComp {
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if (js.HasUnknownPrefix())
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DISABLE;
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// Vector compare
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// VFPU_CC[N] = COMPARE(s[N], t[N])
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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@ -1370,7 +1438,9 @@ namespace MIPSComp {
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DISABLE;
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}
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// logBlocks = 1;
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// Vector conditional move
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// imm3 >= 6: d[N] = VFPU_CC[N] == tf ? s[N] : d[N]
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// imm3 < 6: d[N] = VFPU_CC[imm3] == tf ? s[N] : d[N]
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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@ -1406,6 +1476,9 @@ namespace MIPSComp {
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if (js.HasUnknownPrefix())
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DISABLE;
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// Vector integer immediate
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// d[0] = float(imm)
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s32 imm = (s32)(s16)(u16)(op & 0xFFFF);
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u8 dreg;
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GetVectorRegsPrefixD(&dreg, V_Single, _VT);
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@ -1418,6 +1491,9 @@ namespace MIPSComp {
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if (js.HasUnknownPrefix())
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DISABLE;
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// Vector half-float immediate
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// d[0] = float(imm)
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FP16 half;
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half.u = op & 0xFFFF;
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FP32 fval = half_to_float_fast5(half);
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@ -1430,10 +1506,12 @@ namespace MIPSComp {
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void IRFrontend::Comp_Vcst(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix())
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DISABLE;
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// Vector constant
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// d[N] = CONST
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int conNum = (op >> 16) & 0x1f;
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int vd = _VD;
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@ -1455,6 +1533,14 @@ namespace MIPSComp {
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}
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void IRFrontend::Comp_Vsgn(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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if (js.HasUnknownPrefix()) {
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DISABLE;
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}
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// Vector extract sign
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// d[N] = signum(s[N])
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DISABLE;
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}
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@ -1496,6 +1582,12 @@ namespace MIPSComp {
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}
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void IRFrontend::Comp_ColorConv(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// TODO: Verify if this ignores prefixes?
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// Vector color conversion
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// d[N] = ConvertTo16(s[N*2]) | (ConvertTo16(s[N*2+1]) << 16)
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DISABLE;
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}
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