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Merge branch 'armjit-fpu' of github.com:hrydgard/ppsspp into armjit-fpu

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This commit is contained in:
Henrik Rydgard 2013-03-01 18:26:36 +01:00
commit 253396666c
3 changed files with 105 additions and 57 deletions
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64
Common/ArmEmitter.cpp
View File

@ -766,7 +766,7 @@ void ARMXEmitter::VSTR(ARMReg Src, ARMReg Base, u16 offset)
| ((Src & 0xF) << 12) | (11 << 8) | (offset >> 2)); | ((Src & 0xF) << 12) | (11 << 8) | (offset >> 2));
} }
} }
void ARMXEmitter::VCMP(ARMReg Vd, ARMReg Vm) void ARMXEmitter::VCMP(ARMReg Vd, ARMReg Vm, bool E)
{ {
_assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP"); _assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP");
bool single_reg = Vd < D0; bool single_reg = Vd < D0;
@ -777,15 +777,15 @@ void ARMXEmitter::VCMP(ARMReg Vd, ARMReg Vm)
if (single_reg) if (single_reg)
{ {
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x34 << 16) | ((Vd & 0x1E) << 11) \ Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x34 << 16) | ((Vd & 0x1E) << 11) \
| (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1)); | (E << 7) | (0x29 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
} }
else else
{ {
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x34 << 16) | ((Vd & 0xF) << 12) \ Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x34 << 16) | ((Vd & 0xF) << 12) \
| (0x2F << 6) | ((Vm & 0x10) << 1) | (Vm & 0xF)); | (E << 7) | (0x2C << 6) | ((Vm & 0x10) << 1) | (Vm & 0xF));
} }
} }
void ARMXEmitter::VCMP(ARMReg Vd) void ARMXEmitter::VCMP(ARMReg Vd, bool E)
{ {
_assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP"); _assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP");
bool single_reg = Vd < D0; bool single_reg = Vd < D0;
@ -795,12 +795,12 @@ void ARMXEmitter::VCMP(ARMReg Vd)
if (single_reg) if (single_reg)
{ {
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x35 << 16) | ((Vd & 0x1E) << 11) \ Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x35 << 16) | ((Vd & 0x1E) << 11) \
| (0x2B << 6)); | (E << 7) | (0x29 << 6));
} }
else else
{ {
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x35 << 16) | ((Vd & 0xF) << 12) \ Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x35 << 16) | ((Vd & 0xF) << 12) \
| (0x2F << 6)); | (E << 7) | (0x2C << 6));
} }
} }
void ARMXEmitter::VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm) void ARMXEmitter::VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm)
@ -948,22 +948,47 @@ void ARMXEmitter::VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm)
} }
else else
{ {
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VADD with Quad Reg without support!"); _assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VMUL with Quad Reg without support!");
//Write32((0xF2 << 24) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16)
// | ((Vd & 0xF) << 12) | (0xD << 8) | ((Vn & 0x10) << 3)
// | (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
} }
} }
} }
void ARMXEmitter::VABS(ARMReg Vd, ARMReg Vn) void ARMXEmitter::VABS(ARMReg Vd, ARMReg Vm)
{ {
_assert_msg_(DYNA_REC, 0, "VABS not implemented"); bool single_reg = Vd < D0;
Vd = SubBase(Vd);
Vm = SubBase(Vm);
if (single_reg)
{
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x30 << 16) \
| ((Vd & 0x1E) << 11) | (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
}
else
{
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x30 << 16) \
| ((Vd & 0xF) << 12) | (0x2F << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
}
} }
void ARMXEmitter::VNEG(ARMReg Vd, ARMReg Vn) void ARMXEmitter::VNEG(ARMReg Vd, ARMReg Vm)
{ {
_assert_msg_(DYNA_REC, 0, "VNEG not implemented"); bool single_reg = Vd < D0;
Vd = SubBase(Vd);
Vm = SubBase(Vm);
if (single_reg)
{
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
| ((Vd & 0x1E) << 11) | (0x29 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
}
else
{
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
| ((Vd & 0xF) << 12) | (0x2D << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
}
} }
void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high) void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high)
@ -1060,4 +1085,15 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
} }
} }
void ARMXEmitter::VCVT(ARMReg Sd, ARMReg Sm, bool to_integer, bool is_signed, bool round_to_zero)
{
bool op = to_integer ? round_to_zero : is_signed;
bool op2 = to_integer ? is_signed : 0;
Sd = SubBase(Sd);
Sm = SubBase(Sm);
Write32(NO_COND | (0x1D << 23) | ((Sd & 0x1) << 22) | (0x7 << 19) | (to_integer << 18) | (op2 << 16) \
| ((Sd & 0x1E) << 11) | (op << 7) | (0x29 << 6) | ((Sm & 0x1) << 5) | (Sm >> 1));
}
} }

9
Common/ArmEmitter.h
View File

@ -514,20 +514,21 @@ public:
// VFP Only // VFP Only
void VLDR(ARMReg Dest, ARMReg Base, u16 offset); void VLDR(ARMReg Dest, ARMReg Base, u16 offset);
void VSTR(ARMReg Src, ARMReg Base, u16 offset); void VSTR(ARMReg Src, ARMReg Base, u16 offset);
void VCMP(ARMReg Vd, ARMReg Vm); void VCMP(ARMReg Vd, ARMReg Vm, bool E);
// Compares against zero // Compares against zero
void VCMP(ARMReg Vd); void VCMP(ARMReg Vd, bool E);
void VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm); void VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VSQRT(ARMReg Vd, ARMReg Vm); void VSQRT(ARMReg Vd, ARMReg Vm);
// NEON and VFP // NEON and VFP
void VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm); void VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm); void VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VABS(ARMReg Vd, ARMReg Vn); void VABS(ARMReg Vd, ARMReg Vm);
void VNEG(ARMReg Vd, ARMReg Vn); void VNEG(ARMReg Vd, ARMReg Vm);
void VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm); void VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VMOV(ARMReg Dest, ARMReg Src, bool high); void VMOV(ARMReg Dest, ARMReg Src, bool high);
void VMOV(ARMReg Dest, ARMReg Src); void VMOV(ARMReg Dest, ARMReg Src);
void VCVT(ARMReg Sd, ARMReg Sm, bool to_integer, bool is_signed, bool round_to_zero = false);
void QuickCallFunction(ARMReg scratchreg, void *func); void QuickCallFunction(ARMReg scratchreg, void *func);
// Utility functions // Utility functions

89
Core/MIPS/ARM/ArmCompFPU.cpp
View File

@ -108,7 +108,8 @@ void Jit::Comp_FPUComp(u32 op) {
switch (op & 0xf) { switch (op & 0xf) {
case 0: //f case 0: //f
case 8: //sf case 8: //sf
// MOV(32, M((void *) &currentMIPS->fpcond), Imm32(0)); /*MOVI2R(R0, (u32)&currentMIPS->fpcond);
MOV(R0, Operand2(0));*/
break; break;
case 1: //un case 1: //un
@ -138,7 +139,16 @@ void Jit::Comp_FPUComp(u32 op) {
case 6: //ole case 6: //ole
case 14: //le case 14: //le
// CompFPComp(fs, ft, CMPLESS); // This VCMP crashes on ARM11 with an exception.
/*
fpr.MapInIn(fpr.R(fs), fpr.R(ft));
VCMP(fpr.R(fs), fpr.R(ft));
MOVI2R(R0, (u32)&currentMIPS->fpcond);
SetCC(CC_LT);
// TODO: Should set R0 to 0 or 1
VSTR(fpr.R(fs), R0, 0);
SetCC(CC_AL);
*/
break; break;
case 7: //ule case 7: //ule
@ -161,51 +171,52 @@ void Jit::Comp_FPU2op(u32 op)
switch (op & 0x3f) switch (op & 0x3f)
{ {
/* case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
case 5: //F(fd) = fabsf(F(fs)); break; //abs
fpr.Lock(fd, fs);
fpr.BindToRegister(fd, fd == fs, true);
MOVSS(fpr.R(fd), fpr.R(fs));
PAND(fpr.R(fd), M((void *)ssNoSignMask));
fpr.UnlockAll();
break;
*/
case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
fpr.MapDirtyIn(fd, fs); fpr.MapDirtyIn(fd, fs);
VSQRT(fpr.R(fd), fpr.R(fs)); VSQRT(fpr.R(fd), fpr.R(fs));
return; break;
case 5: //F(fd) = fabsf(F(fs)); break; //abs
fpr.MapDirtyIn(fd, fs);
case 6: //F(fd) = F(fs); break; //mov VABS(fpr.R(fd), fpr.R(fs));
break;
case 6: //F(fd) = F(fs); break; //mov
fpr.MapDirtyIn(fd, fs); fpr.MapDirtyIn(fd, fs);
VMOV(fpr.R(fd), fpr.R(fs)); VMOV(fpr.R(fd), fpr.R(fs));
break; break;
case 7: //F(fd) = -F(fs); break; //neg
/* fpr.MapDirtyIn(fd, fs);
case 7: //F(fd) = -F(fs); break; //neg VNEG(fpr.R(fd), fpr.R(fs));
fpr.Lock(fd, fs);
fpr.BindToRegister(fd, fd == fs, true);
MOVSS(fpr.R(fd), fpr.R(fs));
PXOR(fpr.R(fd), M((void *)ssSignBits2));
fpr.UnlockAll();
break; break;
case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
fpr.MapDirtyIn(fd, fs);
case 13: //FsI(fd) = F(fs)>=0 ? (int)floorf(F(fs)) : (int)ceilf(F(fs)); break;//trunc.w.s VCVT(fpr.R(fd), fpr.R(fs), true, true, false);
fpr.Lock(fs, fd); break;
fpr.StoreFromRegister(fd); case 13: //FsI(fd) = Rto0(F(fs))); break; //trunc.w.s
CVTTSS2SI(EAX, fpr.R(fs)); fpr.MapDirtyIn(fd, fs);
MOV(32, fpr.R(fd), R(EAX)); VCVT(fpr.R(fd), fpr.R(fs), true, true, true);
fpr.UnlockAll(); break;
case 14: //FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
fpr.MapDirtyIn(fd, fs);
MOVI2R(R0, 0x3F000000); // 0.5f
VMOV(S0, R0);
VADD(S0,fpr.R(fs),S0);
VCVT(fpr.R(fd), S0, true, true, false);
break;
case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
fpr.MapDirtyIn(fd, fs);
MOVI2R(R0, 0x3F000000); // 0.5f
VMOV(S0, R0);
VSUB(S0,fpr.R(fs),S0);
VCVT(fpr.R(fd), S0, true, true, false);
break;
case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
fpr.MapDirtyIn(fd, fs);
VCVT(fpr.R(fd), fpr.R(fs), false, true);
break;
case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
fpr.MapDirtyIn(fd, fs);
VCVT(fpr.R(fd), fpr.R(fs), true, false, true);
break; break;
case 14: //FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
*/
default: default:
DISABLE; DISABLE;
} }