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Add VFPU instructions to the mips asm tables.
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@ -105,6 +105,81 @@ int MipsGetFloatRegister(const char* source, int& RetLen)
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return -1;
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}
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int MipsGetVectorRegister(const char* source, int& RetLen)
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{
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// Syntax: <type> <matrix> <col> <row>
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int transpose;
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switch (source[0])
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{
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case 's':
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case 'S':
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case 'c':
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case 'C':
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case 'm':
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case 'M':
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transpose = 0;
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break;
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case 'r':
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case 'R':
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case 'e':
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case 'E':
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transpose = 1;
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break;
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default:
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return -1;
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}
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if (source[1] < '0' || source[1] > '7')
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return -1;
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if (source[2] < '0' || source[2] > '3')
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return -1;
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if (source[3] < '0' || source[3] > '3')
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return -1;
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if (source[4] == ',' || source[4] == '\n' || source[4] == 0
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|| source[4] == ')' || source[4] == '(' || source[4] == '-') // one of these HAS TO come after a register
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{
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RetLen = 4;
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// Now to encode it.
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int mtx = source[1] - '0';
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int col = source[2] - '0';
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int row = source[3] - '0';
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// Encoding: S: RRMMMCC, anything else: RTMMMCC (T indicates tranposem swao CC and R.)
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// More could be done to verify these are valid, though (and against the opcode.)
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// For example, S must be used for S regs, but also C033 is not ever valid.
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if (source[0] == 'S')
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return (row << 5) | (mtx << 2) | col;
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else if (transpose)
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return ((col != 0) << 6) | (1 << 5) | (mtx << 2) | row;
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else
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return ((row != 0) << 6) | (0 << 5) | (mtx << 2) | col;
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}
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return -1;
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}
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int MIPSGetVectorCondition(const char* source, int& RetLen)
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{
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if (source[0] == 0 || source[1] == 0)
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return -1;
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if (source[2] == ',' || source[2] == '\n' || source[2] == 0
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|| source[2] == ')' || source[2] == '(' || source[2] == '-')
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{
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static const char *conditions[] = {"FL", "EQ", "LT", "LE", "TR", "NE", "GE", "GT", "EZ", "EN", "EI", "ES", "NZ", "NN", "NI", "NS"};
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for (int i = 0; i < (int)ARRAY_SIZE(conditions); ++i)
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{
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if (source[0] == conditions[i][0] && source[1] == conditions[i][1])
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{
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RetLen = 2;
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return i;
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}
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}
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}
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return -1;
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}
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bool MipsCheckImmediate(const char* Source, char* Dest, int& RetLen)
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{
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int BufferPos = 0;
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@ -198,6 +273,7 @@ bool CMipsInstruction::LoadEncoding(const tMipsOpcode& SourceOpcode, char* Line)
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int RetLen;
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bool Immediate = false;
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bool NextVector = false;
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const char *SourceEncoding = SourceOpcode.encoding;
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char* OriginalLine = Line;
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@ -213,18 +289,28 @@ bool CMipsInstruction::LoadEncoding(const tMipsOpcode& SourceOpcode, char* Line)
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switch (*SourceEncoding)
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{
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case 'V': // vector prefix
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NextVector = true;
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SourceEncoding++;
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break;
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case 'T': // float reg
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if ((Vars.rt = MipsGetFloatRegister(Line,RetLen)) == -1) return false;
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Vars.rt = NextVector ? MipsGetVectorRegister(Line, RetLen) : MipsGetFloatRegister(Line, RetLen);
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NextVector = false;
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if (Vars.rt == -1) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'D': // float reg
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if ((Vars.rd = MipsGetFloatRegister(Line,RetLen)) == -1) return false;
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Vars.rd = NextVector ? MipsGetVectorRegister(Line, RetLen) : MipsGetFloatRegister(Line, RetLen);
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NextVector = false;
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if (Vars.rd == -1) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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case 'S': // float reg
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if ((Vars.rs = MipsGetFloatRegister(Line,RetLen)) == -1) return false;
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Vars.rs = NextVector ? MipsGetVectorRegister(Line, RetLen) : MipsGetFloatRegister(Line, RetLen);
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NextVector = false;
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if (Vars.rs == -1) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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@ -257,6 +343,11 @@ bool CMipsInstruction::LoadEncoding(const tMipsOpcode& SourceOpcode, char* Line)
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Line += RetLen;
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SourceEncoding += 2;
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break;
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case 'C':
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if ((Vars.Condition = MIPSGetVectorCondition(Line, RetLen)) == -1) return false;
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Line += RetLen;
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SourceEncoding++;
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break;
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default: // everything else
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if (*SourceEncoding++ != *Line++) return false;
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break;
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@ -290,6 +381,9 @@ bool CMipsInstruction::LoadEncoding(const tMipsOpcode& SourceOpcode, char* Line)
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} else if (Opcode.flags & O_I26)
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{
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Vars.ImmediateType = MIPS_IMMEDIATE26;
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} else if (Opcode.flags & MO_VIMM)
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{
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Vars.ImmediateType = MIPS_IMMEDIATE8;
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}
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} else {
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Vars.ImmediateType = MIPS_NOIMMEDIATE;
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@ -359,6 +453,15 @@ bool CMipsInstruction::Validate()
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}
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Vars.Immediate &= 0x03FFFFFF;
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break;
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case MIPS_IMMEDIATE8:
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// TODO: Validate better, or more types.
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if (abs(Vars.Immediate) > 0x000000FF)
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{
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SetAssembleError("Immediate value %08X out of range",Vars.OriginalImmediate);
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return false;
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}
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Vars.Immediate &= 0x000000FF;
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break;
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case MIPS_NOIMMEDIATE:
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break;
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}
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@ -392,7 +495,7 @@ void CMipsInstruction::Encode()
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if (Opcode.flags & MO_FRT) encoding |= (Vars.rt << 16); // float target
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if (Opcode.flags & MO_FRS) encoding |= (Vars.rs << 11); // float source
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if (Opcode.flags & MO_FRD) encoding |= (Vars.rd << 6); // float target
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if (Opcode.flags & MO_FRD) encoding |= (Vars.rd << 6); // float dest
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if (Opcode.flags & MO_FRSD) // s = d & s
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{
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encoding |= (Vars.rs << 6);
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@ -409,6 +512,12 @@ void CMipsInstruction::Encode()
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encoding |= (Vars.rd << 16);
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}
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if (Opcode.flags & MO_VRT) encoding |= (Vars.rt << 16); // vector target
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if (Opcode.flags & MO_VRS) encoding |= (Vars.rs << 8); // vector source
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if (Opcode.flags & MO_VRD) encoding |= (Vars.rd << 0); // vector dest
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if (Opcode.flags & MO_VRTI) encoding |= ((Vars.rt & 0x1f) << 16) | (Vars.rt >> 5);
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if (Opcode.flags & MO_VCOND) encoding |= (Vars.Condition << 0); // vector dest
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switch (Vars.ImmediateType)
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{
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case MIPS_IMMEDIATE5:
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@ -423,6 +532,9 @@ void CMipsInstruction::Encode()
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case MIPS_IMMEDIATE26:
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encoding |= (Vars.Immediate & 0x03FFFFFF);
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break;
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case MIPS_IMMEDIATE8:
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encoding |= (Vars.Immediate & 0x000000FF) << 16;
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break;
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case MIPS_NOIMMEDIATE:
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break;
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}
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@ -8,7 +8,7 @@ namespace MIPSAsm {
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bool MipsAssembleOpcode(const char* line, DebugInterface* cpu, u32 address, u32& dest);
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enum eMipsImmediateType { MIPS_NOIMMEDIATE, MIPS_IMMEDIATE5,
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MIPS_IMMEDIATE16, MIPS_IMMEDIATE20, MIPS_IMMEDIATE26 };
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MIPS_IMMEDIATE16, MIPS_IMMEDIATE20, MIPS_IMMEDIATE26, MIPS_IMMEDIATE8 };
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typedef struct {
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int rs; // source reg
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@ -17,6 +17,7 @@ typedef struct {
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eMipsImmediateType ImmediateType;
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int Immediate;
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int OriginalImmediate;
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int Condition;
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} tMipsOpcodeVariables;
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class CMipsInstruction
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@ -94,6 +94,8 @@ const tMipsRegister MipsFloatRegister[] = {
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n negative 16 bit immediate (for subi/u aliases)
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b 26 bit immediate
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a 5 bit immediate
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V prefix for S, D, T indicating vector register
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C vector compare condition (EQ, etc.)
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*/
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const tMipsOpcode MipsOpcodes[] = {
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@ -255,14 +257,14 @@ const tMipsOpcode MipsOpcodes[] = {
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{ "blezl", "s,I", 0x58000000, O_RS|O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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// OPCODE 17 - BGTZL MIPS 2
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{ "bgtzl", "s,I", 0x5c000000, O_RS|O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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// OPCODE 18 - UNDEF
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// OPCODE 19 - UNDEF
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// OPCODE 18 - VFPU0
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// OPCODE 19 - VFPU1
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// OPCODE 1A - UNDEF
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// OPCODE 1B - UNDEF
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// OPCODE 1C - UNDEF
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// OPCODE 1B - VFPU3
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// OPCODE 1C - SPECIAL2
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// OPCODE 1D - UNDEF
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// OPCODE 1E - UNDEF
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// OPCODE 1F - UNDEF
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// OPCODE 1F - SPECIAL3
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// OPCODE 20 - LB
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{ "lb", "t,i(s)", 0x80000000, O_RT|O_I16|O_RS|MO_DELAYRT },
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{ "lb", "t,(s)", 0x80000000, O_RT|O_RS|MO_DELAYRT },
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@ -302,27 +304,49 @@ const tMipsOpcode MipsOpcodes[] = {
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// OPCODE 2E - SWR
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{ "swr", "t,i(s)", 0xb8000000, O_RT|O_I16|O_RS },
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{ "swr", "t,(s)", 0xb8000000, O_RT|O_RS },
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// OPCODE 2F - UNDEF
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// OPCODE 30 - UNDEF
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// OPCODE 2F - CACHE
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// OPCODE 30 - LL
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{ "ll", "t,i(s)", 0xc0000000, O_RT|O_I16|O_RS|MO_DELAYRT },
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{ "ll", "t,(s)", 0xc0000000, O_RT|O_RS|MO_DELAYRT },
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// OPCODE 31 - LWC1
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{ "lwc1", "T,i(s)", 0xc4000000, MO_FRT|O_I16|O_RS },
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// OPCODE 32 - LWC2
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{ "lwc2", "T,i(s)", 0xc8000000, MO_FRT|O_I16|O_RS },
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{ "lwc1", "T,(s)", 0xc4000000, MO_FRT|O_RS },
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// OPCODE 32 - LVS - VVVVVV SSSSS TTTTT IIIIIIIIIIIIII TT
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{ "lwc2", "VT,i(s)", 0xc8000000, MO_VRTI|O_I16|O_RS },
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{ "lwc2", "VT,(s)", 0xc8000000, MO_VRTI|O_RS },
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{ "lv.s", "VT,i(s)", 0xc8000000, MO_VRTI|O_I16|O_RS },
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{ "lv.s", "VT,(s)", 0xc8000000, MO_VRTI|O_RS },
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// OPCODE 33 - LWC3
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// OPCODE 34 - UNDEF
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// OPCODE 35 - UNDEF
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// OPCODE 36 - UNDEF
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// OPCODE 37 - UNDEF
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// OPCODE 38 - UNDEF
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// OPCODE 34 - VFPU4
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// OPCODE 35 - ULVQ - VVVVVV SSSSS TTTTT IIIIIIIIIIIIII TT (WARNING: reportedly buggy on PSP-1000)
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{ "ulv.q", "VT,i(s)", 0xd4000000, MO_VRTI|O_I16|O_RS },
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{ "lvl.q", "VT,i(s)", 0xd4000000, MO_VRTI|O_I16|O_RS },
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{ "lvr.q", "VT,i(s)", 0xd4000002, MO_VRTI|O_I16|O_RS },
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// OPCODE 36 - LVQ
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{ "lv.q", "VT,i(s)", 0xd8000000, MO_VRTI|O_I16|O_RS },
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{ "lv.q", "VT,(s)", 0xd8000000, MO_VRTI|O_RS },
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// OPCODE 37 - VFPU5
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// OPCODE 38 - SC
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{ "sc", "t,i(s)", 0xe0000000, O_RT|O_I16|O_RS },
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{ "sc", "t,(s)", 0xe0000000, O_RT|O_RS },
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// OPCODE 39 - SWC1
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{ "swc1", "T,i(s)", 0xe4000000, MO_FRT|O_I16|O_RS },
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// OPCODE 3A - SWC2
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{ "swc2", "T,i(s)", 0xe8000000, MO_FRT|O_I16|O_RS },
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{ "swc1", "T,(s)", 0xe4000000, MO_FRT|O_I16|O_RS },
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// OPCODE 3A - SVS - VVVVVV SSSSS TTTTT IIIIIIIIIIIIII TT
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{ "swc2", "VT,i(s)", 0xe8000000, MO_VRTI|O_I16|O_RS },
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{ "swc2", "VT,(s)", 0xe8000000, MO_VRTI|O_RS },
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{ "sv.s", "VT,i(s)", 0xe8000000, MO_VRTI|O_I16|O_RS },
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{ "sv.s", "VT,(s)", 0xe8000000, MO_VRTI|O_RS },
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// OPCODE 3B - SWC3
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// OPCODE 3C - UNDEF
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// OPCODE 3D - UNDEF
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// OPCODE 3E - UNDEF
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// OPCODE 3F - UNDEF
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// OPCODE 3C - VFPU6
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// OPCODE 3D - USVQ - VVVVVV SSSSS TTTTT IIIIIIIIIIIIII TT
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{ "usv.q", "VT,i(s)", 0xf4000000, MO_VRTI|O_I16|O_RS },
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{ "svl.q", "VT,i(s)", 0xf4000000, MO_VRTI|O_I16|O_RS },
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{ "svr.q", "VT,i(s)", 0xf4000002, MO_VRTI|O_I16|O_RS },
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// OPCODE 3E - SVQ - VVVVVV SSSSS TTTTT IIIIIIIIIIIIII TT
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{ "sv.q", "VT,i(s)", 0xf8000000, MO_VRTI|O_I16|O_RS },
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{ "sv.q", "VT,(s)", 0xf8000000, MO_VRTI|O_RS },
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// OPCODE 3F - VFPU7
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// 31-------26------21---------------------------------------------0
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@ -416,7 +440,277 @@ const tMipsOpcode MipsOpcodes[] = {
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// hi |-------|-------|-------|-------|-------|-------|-------|-------|
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{ "cvt.s.w", "D,S", 0x46800020, MO_FRD|MO_FRS },
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// 31-------26------21---------------------------------------------0
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// |= COP2| rs | |
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// -----6-------5---------------------------------------------------
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
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// 00 | --- | --- | --- | MFV | --- | --- | --- | MTV |
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// 01 | BC* | --- | --- | --- | --- | --- | --- | --- |
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// 10 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 11 | --- | --- | --- | --- | --- | --- | --- | --- |
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// hi |-------|-------|-------|-------|-------|-------|-------|-------|
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// VVVVVV VVVVV ttttt -------- C DDDDDDD
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{ "mfv", "t,VD", MIPS_COP2(3), MO_VRD|O_RT },
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{ "mfvc", "t,i", MIPS_COP2(3) | 0x80, O_I16|O_RT },
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{ "mtv", "t,VD", MIPS_COP2(7), MO_VRD|O_RT },
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{ "mtvc", "t,i", MIPS_COP2(7) | 0x80, O_I16|O_RT },
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// COP2BC: ? indicates any, * indicates all
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// 31---------21-------16------------------------------------------0
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// |= COP2BC| rt | |
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// ------11---------5-----------------------------------------------
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
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// 00 | BVFx | BVTx | BVFLx | BVTLx | BVFy | BVTy | BVFLy | BVTLy |
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// 01 | BVFz | BVTz | BVFLz | BVTLz | BVFw | BVTw | BVFLw | BVTLw |
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// 10 | BVF? | BVT? | BVFL? | BVTL? | BVF* | BVT* | BVFL* | BVTL* |
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// 11 | --- | --- | --- | --- | --- | --- | --- | --- |
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// hi |-------|-------|-------|-------|-------|-------|-------|-------|
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// TODO: Multiple immediates (format: bvf 0, label)...? We'll just use .x for now.
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// VVVVVV VVVVV iii L C IIIIIIIIIIIIIIII
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{ "bvf.x", "I", MIPS_COP2BC(0x00), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvt.x", "I", MIPS_COP2BC(0x01), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvfl.x", "I", MIPS_COP2BC(0x02), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvtl.x", "I", MIPS_COP2BC(0x03), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvf.y", "I", MIPS_COP2BC(0x04), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvt.y", "I", MIPS_COP2BC(0x05), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvfl.y", "I", MIPS_COP2BC(0x06), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvtl.y", "I", MIPS_COP2BC(0x07), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvf.z", "I", MIPS_COP2BC(0x08), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvt.z", "I", MIPS_COP2BC(0x09), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvfl.z", "I", MIPS_COP2BC(0x0a), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvtl.z", "I", MIPS_COP2BC(0x0b), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
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{ "bvf.w", "I", MIPS_COP2BC(0x0c), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvt.w", "I", MIPS_COP2BC(0x0d), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvfl.w", "I", MIPS_COP2BC(0x0e), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvtl.w", "I", MIPS_COP2BC(0x0f), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvf.any", "I", MIPS_COP2BC(0x10), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvt.any", "I", MIPS_COP2BC(0x11), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvfl.any", "I", MIPS_COP2BC(0x12), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvtl.any", "I", MIPS_COP2BC(0x13), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvf.all", "I", MIPS_COP2BC(0x14), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvt.all", "I", MIPS_COP2BC(0x15), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvfl.all", "I", MIPS_COP2BC(0x16), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
{ "bvtl.all", "I", MIPS_COP2BC(0x17), O_I16|O_IPCR|MO_DELAY|MO_NODELAY },
|
||||
|
||||
// 31-------26-----23----------------------------------------------0
|
||||
// |= VFPU0| f | |
|
||||
// -----6-------3---------------------------------------------------
|
||||
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
|
||||
// | VADD | VSUB | VSBN | --- | --- | --- | --- | VDIV |
|
||||
// |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV VVV TTTTTTT z SSSSSSS z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vadd", "VD,VS,VT", MIPS_VFPU0(0), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vsub", "VD,VS,VT", MIPS_VFPU0(1), MO_VRD|MO_VRS|MO_VRT),
|
||||
// Including encodings that may work but aren't technically valid/sane for easy testing.
|
||||
// TODO: Could remove or warn?
|
||||
MIPS_VFPU_ALLSIZES("vsbn", "VD,VS,VT", MIPS_VFPU0(2), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vdiv", "VD,VS,VT", MIPS_VFPU0(7), MO_VRD|MO_VRS|MO_VRT),
|
||||
|
||||
// 31-------26-----23----------------------------------------------0
|
||||
// |= VFPU1| f | |
|
||||
// -----6-------3---------------------------------------------------
|
||||
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
|
||||
// | VMUL | VDOT | VSCL | --- | VHDP | VDET | VCRS | --- |
|
||||
// |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV VVV TTTTTTT z SSSSSSS z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vmul", "VD,VS,VT", MIPS_VFPU1(0), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vdot", "VD,VS,VT", MIPS_VFPU1(1), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vscl", "VD,VS,VT", MIPS_VFPU1(2), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vhdp", "VD,VS,VT", MIPS_VFPU1(4), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vdet", "VD,VS,VT", MIPS_VFPU1(5), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vcrs", "VD,VS,VT", MIPS_VFPU1(6), MO_VRD|MO_VRS|MO_VRT),
|
||||
|
||||
// 31-------26-----23----------------------------------------------0
|
||||
// |= VFPU3| f | |
|
||||
// -----6-------3---------------------------------------------------
|
||||
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
|
||||
// | VCMP | --- | VMIN | VMAX | --- | VSCMP | VSGE | VSLT |
|
||||
// |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV VVV TTTTTTT z SSSSSSS z --- CCCC
|
||||
MIPS_VFPU_ALLSIZES("vcmp", "C,VS,VT", MIPS_VFPU3(0), MO_VRS|MO_VRT|MO_VCOND),
|
||||
// VVVVVV VVV TTTTTTT z SSSSSSS z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vmin", "VD,VS,VT", MIPS_VFPU3(2), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vmax", "VD,VS,VT", MIPS_VFPU3(3), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vscmp", "VD,VS,VT", MIPS_VFPU3(5), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vsge", "VD,VS,VT", MIPS_VFPU3(6), MO_VRD|MO_VRS|MO_VRT),
|
||||
MIPS_VFPU_ALLSIZES("vslt", "VD,VS,VT", MIPS_VFPU3(7), MO_VRD|MO_VRS|MO_VRT),
|
||||
|
||||
// 31-------26--------------------------------------------5--------0
|
||||
// |=SPECIAL3| | function|
|
||||
// -----11----------------------------------------------------6-----
|
||||
// -----6-------5---------------------------------------------------
|
||||
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
// 000 | EXT | --- | --- | --- | INS | --- | --- | --- |
|
||||
// 001 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
// 010 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
// 011 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
// 100 |ALLEGRE| --- | --- | --- | --- | --- | --- | --- |
|
||||
// 101 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
// 110 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
// 110 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV sssss ttttt zzzzz ppppp VVVVVV
|
||||
// TODO: This has two immediates, size (z) and pos (p)...
|
||||
|
||||
// 31-------26----------------------------------10--------5--------0
|
||||
// |=SPECIAL3| | secfunc |ALLEGREX0|
|
||||
// ------11---------5-------------------------------5---------6-----
|
||||
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
// 00 | --- | --- | WSBH | WSBW | --- | --- | --- | --- |
|
||||
// 01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
// 10 | SEB | --- | --- | --- |BITREV | --- | --- | --- |
|
||||
// 11 | SEH | --- | --- | --- | --- | --- | --- | --- |
|
||||
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV ----- ttttt ddddd VVVVV VVVVVV
|
||||
{ "wsbh", "d,t", MIPS_ALLEGREX0(0x02), O_RD|O_RT },
|
||||
{ "wsbh", "d", MIPS_ALLEGREX0(0x02), O_RDT },
|
||||
{ "wsbw", "d,t", MIPS_ALLEGREX0(0x03), O_RD|O_RT },
|
||||
{ "wsbw", "d", MIPS_ALLEGREX0(0x03), O_RDT },
|
||||
{ "seb", "d,t", MIPS_ALLEGREX0(0x10), O_RD|O_RT },
|
||||
{ "seb", "d", MIPS_ALLEGREX0(0x10), O_RDT },
|
||||
{ "bitrev", "d,t", MIPS_ALLEGREX0(0x14), O_RD|O_RT },
|
||||
{ "bitrev", "d", MIPS_ALLEGREX0(0x14), O_RDT },
|
||||
{ "seh", "d,t", MIPS_ALLEGREX0(0x18), O_RD|O_RT },
|
||||
{ "seh", "d", MIPS_ALLEGREX0(0x18), O_RDT },
|
||||
|
||||
// VFPU4: This one is a bit messy.
|
||||
// 31-------26------21---------------------------------------------0
|
||||
// |= VFPU4| rs | |
|
||||
// -----6-------5---------------------------------------------------
|
||||
// hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
// 00 |VF4-1.1|VF4-1.2|VF4-1.3| VCST | --- | --- | --- | --- |
|
||||
// 01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
// 10 | VF2IN | VF2IZ | VF2IU | VF2ID | VI2F | VCMOV | --- | --- |
|
||||
// 11 | VWBN | VWBN | VWBN | VWBN | VWBN | VWBN | VWBN | VWBN |
|
||||
// |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV VVVVV iiiii z ------- z DDDDDDD
|
||||
// Technically these also have names (as the second arg.)
|
||||
MIPS_VFPU_ALLSIZES("vcst", "VD,i", MIPS_VFPU4(0x03), MO_VRD|MO_VIMM),
|
||||
// VVVVVV VVVVV iiiii z SSSSSSS z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vf2in", "VD,VS,i", MIPS_VFPU4(0x10), MO_VRD|MO_VRS|MO_VIMM),
|
||||
MIPS_VFPU_ALLSIZES("vf2iz", "VD,VS,i", MIPS_VFPU4(0x11), MO_VRD|MO_VRS|MO_VIMM),
|
||||
MIPS_VFPU_ALLSIZES("vf2iu", "VD,VS,i", MIPS_VFPU4(0x12), MO_VRD|MO_VRS|MO_VIMM),
|
||||
MIPS_VFPU_ALLSIZES("vf2id", "VD,VS,i", MIPS_VFPU4(0x13), MO_VRD|MO_VRS|MO_VIMM),
|
||||
MIPS_VFPU_ALLSIZES("vi2f", "VD,VS,i", MIPS_VFPU4(0x14), MO_VRD|MO_VRS|MO_VIMM),
|
||||
// VVVVVV VVVVV - C iii z SSSSSSS z DDDDDDD
|
||||
// This is arguably a horrible syntax but it's the common one.
|
||||
MIPS_VFPU_ALLSIZES("vcmovt", "VD,VS,i", MIPS_VFPU4(0x15) | 0x00000000, MO_VRD|MO_VRS|MO_VIMM),
|
||||
MIPS_VFPU_ALLSIZES("vcmovf", "VD,VS,i", MIPS_VFPU4(0x15) | 0x00080000, MO_VRD|MO_VRS|MO_VIMM),
|
||||
// VVVVVV VV iiiiiiii z SSSSSSS z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vwbn", "VD,VS,i", MIPS_VFPU4(0x18), MO_VRD|MO_VRS|MO_VIMM),
|
||||
|
||||
// 31-------------21-------16--------------------------------------0
|
||||
// |= VF4-1.1 | rt | |
|
||||
// --------11----------5--------------------------------------------
|
||||
// hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
// 00 | VMOV | VABS | VNEG | VIDT | VSAT0 | VSAT1 | VZERO | VONE |
|
||||
// 01 | --- | --- | --- | --- | --- | --- | --- | --- |
|
||||
// 10 | VRCP | VRSQ | VSIN | VCOS | VEXP2 | VLOG2 | VSQRT | VASIN |
|
||||
// 11 | VNRCP | --- | VNSIN | --- |VREXP2 | --- | --- | --- |
|
||||
// |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV VVVVV VVVVV z SSSSSSS z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vmov", "VD,VS", MIPS_VFPU4_11(0x00), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vabs", "VD,VS", MIPS_VFPU4_11(0x01), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vneg", "VD,VS", MIPS_VFPU4_11(0x02), MO_VRD|MO_VRS),
|
||||
// VVVVVV VVVVV VVVVV z ------- z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vidt", "VD", MIPS_VFPU4_11(0x03), MO_VRD),
|
||||
// VVVVVV VVVVV VVVVV z SSSSSSS z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vsat0", "VD,VS", MIPS_VFPU4_11(0x04), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vsat1", "VD,VS", MIPS_VFPU4_11(0x05), MO_VRD|MO_VRS),
|
||||
// VVVVVV VVVVV VVVVV z ------- z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vzero", "VD", MIPS_VFPU4_11(0x06), MO_VRD),
|
||||
MIPS_VFPU_ALLSIZES("vone", "VD", MIPS_VFPU4_11(0x07), MO_VRD),
|
||||
// VVVVVV VVVVV VVVVV z SSSSSSS z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vrcp", "VD,VS", MIPS_VFPU4_11(0x10), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vrsq", "VD,VS", MIPS_VFPU4_11(0x11), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vsin", "VD,VS", MIPS_VFPU4_11(0x12), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vcos", "VD,VS", MIPS_VFPU4_11(0x13), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vexp2", "VD,VS", MIPS_VFPU4_11(0x14), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vlog2", "VD,VS", MIPS_VFPU4_11(0x15), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vsqrt", "VD,VS", MIPS_VFPU4_11(0x16), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vasin", "VD,VS", MIPS_VFPU4_11(0x17), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vnrcp", "VD,VS", MIPS_VFPU4_11(0x18), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vnsin", "VD,VS", MIPS_VFPU4_11(0x1a), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vrexp2", "VD,VS", MIPS_VFPU4_11(0x1c), MO_VRD|MO_VRS),
|
||||
|
||||
// VFPU4 1.2: TODO: Unsure where VSBZ goes, no one uses it.
|
||||
// 31-------------21-------16--------------------------------------0
|
||||
// |= VF4-1.2 | rt | |
|
||||
// --------11----------5--------------------------------------------
|
||||
// hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
// 00 | VRNDS | VRNDI |VRNDF1 |VRNDF2 | --- | --- | --- | --- |
|
||||
// 01 | --- | --- | --- | --- | VSBZ? | --- | --- | --- |
|
||||
// 10 | --- | --- | VF2H | VH2F | --- | --- | VSBZ? | VLGB |
|
||||
// 11 | VUC2I | VC2I | VUS2I | VS2I | VI2UC | VI2C | VI2US | VI2S |
|
||||
// |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV VVVVV VVVVV z ------- z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vrnds", "VD", MIPS_VFPU4_12(0x00), MO_VRD),
|
||||
MIPS_VFPU_ALLSIZES("vrndi", "VD", MIPS_VFPU4_12(0x01), MO_VRD),
|
||||
MIPS_VFPU_ALLSIZES("vrndf1", "VD", MIPS_VFPU4_12(0x02), MO_VRD),
|
||||
MIPS_VFPU_ALLSIZES("vrndf2", "VD", MIPS_VFPU4_12(0x03), MO_VRD),
|
||||
// VVVVVV VVVVV VVVVV z SSSSSSS z DDDDDDD
|
||||
// TODO: VSBZ?
|
||||
MIPS_VFPU_ALLSIZES("vf2h", "VD,VS", MIPS_VFPU4_12(0x12), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vh2f", "VD,VS", MIPS_VFPU4_12(0x13), MO_VRD|MO_VRS),
|
||||
// TODO: VSBZ?
|
||||
MIPS_VFPU_ALLSIZES("vlgb", "VD,VS", MIPS_VFPU4_12(0x17), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vuc2i", "VD,VS", MIPS_VFPU4_12(0x18), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vc2i", "VD,VS", MIPS_VFPU4_12(0x19), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vus2i", "VD,VS", MIPS_VFPU4_12(0x1a), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vs2i", "VD,VS", MIPS_VFPU4_12(0x1b), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vi2uc", "VD,VS", MIPS_VFPU4_12(0x1c), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vi2c", "VD,VS", MIPS_VFPU4_12(0x1d), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vi2us", "VD,VS", MIPS_VFPU4_12(0x1e), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vi2s", "VD,VS", MIPS_VFPU4_12(0x1f), MO_VRD|MO_VRS),
|
||||
|
||||
// 31--------------21------16--------------------------------------0
|
||||
// |= VF4-1.3 | rt | |
|
||||
// --------11----------5--------------------------------------------
|
||||
// hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
// 00 | VSRT1 | VSRT2 | VBFY1 | VBFY2 | VOCP | VSOCP | VFAD | VAVG |
|
||||
// 01 | VSRT3 | VSRT4 | VSGN | --- | --- | --- | --- | --- |
|
||||
// 10 | VMFVC | VMTVC | --- | --- | --- | --- | --- | --- |
|
||||
// 11 | --- |VT4444 |VT5551 |VT5650 | --- | --- | --- | --- |
|
||||
// |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV VVVVV VVVVV z SSSSSSS z DDDDDDD
|
||||
MIPS_VFPU_ALLSIZES("vsrt1", "VD,VS", MIPS_VFPU4_13(0x00), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vsrt2", "VD,VS", MIPS_VFPU4_13(0x01), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vbfy1", "VD,VS", MIPS_VFPU4_13(0x02), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vbfy2", "VD,VS", MIPS_VFPU4_13(0x03), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vocp", "VD,VS", MIPS_VFPU4_13(0x04), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vsocp", "VD,VS", MIPS_VFPU4_13(0x05), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vfad", "VD,VS", MIPS_VFPU4_13(0x06), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vavg", "VD,VS", MIPS_VFPU4_13(0x07), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vsrt3", "VD,VS", MIPS_VFPU4_13(0x08), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vsrt4", "VD,VS", MIPS_VFPU4_13(0x09), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vsgn", "VD,VS", MIPS_VFPU4_13(0x0a), MO_VRD|MO_VRS),
|
||||
// VVVVVV VVVVV VVVVV z SSSSSSS iiiiiiii
|
||||
// TODO: Actually a 7-bit imm (top bit is control register flag.)
|
||||
// TODO: Not 100% sure about syntax, or if vmfv is even valid.
|
||||
MIPS_VFPU_ALLSIZES("vmfv", "VS,i", MIPS_VFPU4_13(0x10) | 0x00, MO_VRS|O_I16),
|
||||
MIPS_VFPU_ALLSIZES("vmtv", "VS,i", MIPS_VFPU4_13(0x11) | 0x00, MO_VRD|O_I16),
|
||||
MIPS_VFPU_ALLSIZES("vmfvc", "VS,i", MIPS_VFPU4_13(0x10) | 0x80, MO_VRS|O_I16),
|
||||
MIPS_VFPU_ALLSIZES("vmtvc", "VS,i", MIPS_VFPU4_13(0x11) | 0x80, MO_VRD|O_I16),
|
||||
|
||||
MIPS_VFPU_ALLSIZES("vt4444", "VD,VS", MIPS_VFPU4_13(0x19), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vt5551", "VD,VS", MIPS_VFPU4_13(0x1a), MO_VRD|MO_VRS),
|
||||
MIPS_VFPU_ALLSIZES("vt5650", "VD,VS", MIPS_VFPU4_13(0x1b), MO_VRD|MO_VRS),
|
||||
|
||||
// 31-------26-----23----------------------------------------------0
|
||||
// |= VFPU5| f | |
|
||||
// -----6-------3---------00----------------------------------------
|
||||
// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
|
||||
// | VPFXS | VPFXS | VPFXT | VPFXT | VPFXD | VPFXD | VIIM | VFIM |
|
||||
// |-------|-------|-------|-------|-------|-------|-------|-------|
|
||||
// VVVVVV VV -------- iiiiiiiiiiiiiiii
|
||||
// TODO: This is a whole world of complication for proper syntax. Will allow integer directly for now.
|
||||
{ "vpfxs", "i", MIPS_VFPU5(0), O_I16 },
|
||||
{ "vpfxt", "i", MIPS_VFPU5(2), O_I16 },
|
||||
{ "vpfxd", "i", MIPS_VFPU5(4), O_I16 },
|
||||
// VVVVVV VVV TTTTTTT iiiiiiiiiiiiiiii
|
||||
{ "viim.s", "VT,i", MIPS_VFPU5(6), MO_VRT|O_I16 },
|
||||
// TODO: This should actually encode a half-float, not integer...
|
||||
{ "vfim.s", "VT,i", MIPS_VFPU5(7), MO_VRT|O_I16 },
|
||||
|
||||
|
||||
// END
|
||||
|
||||
@ -40,6 +40,56 @@ typedef struct {
|
||||
#define MO_FRST 0x00400000 // float rs + rt
|
||||
#define MO_FRDT 0x00800000 // float rt + rd
|
||||
|
||||
// TODO: Ideally we should specify the sizes thereof, matrices, etc... too many bits.
|
||||
#define MO_VRS 0x01000000 // vector rs
|
||||
#define MO_VRD 0x02000000 // vector rd
|
||||
#define MO_VRT 0x04000000 // vector rt
|
||||
#define MO_VRTI 0x08000000 // vector rt, used with load/store encodings
|
||||
#define MO_VCOND 0x10000000 // vector condition
|
||||
#define MO_VIMM 0x10000000 // vector 3-8 bit imm
|
||||
|
||||
#define BITFIELD(START,LENGTH,VALUE) (((VALUE) & ((1 << (LENGTH)) - 1)) << (START))
|
||||
#define MIPS_FUNC(VALUE) BITFIELD(0,6,(VALUE))
|
||||
#define MIPS_SA(VALUE) BITFIELD(6,5,(VALUE))
|
||||
#define MIPS_SECFUNC(VALUE) MIPS_SA((VALUE))
|
||||
#define MIPS_OP(VALUE) BITFIELD(26,6,(VALUE))
|
||||
|
||||
#define MIPS_RS(VALUE) BITFIELD(21,5,(VALUE))
|
||||
#define MIPS_RT(VALUE) BITFIELD(16,5,(VALUE))
|
||||
#define MIPS_RD(VALUE) BITFIELD(11,5,(VALUE))
|
||||
#define MIPS_FS(VALUE) MIPS_RD((VALUE))
|
||||
#define MIPS_FT(VALUE) MIPS_RT((VALUE))
|
||||
#define MIPS_FD(VALUE) MIPS_SA((VALUE))
|
||||
|
||||
#define MIPS_SPECIAL(VALUE) (MIPS_OP(0) | MIPS_FUNC(VALUE))
|
||||
#define MIPS_REGIMM(VALUE) (MIPS_OP(1) | MIPS_RT(VALUE))
|
||||
#define MIPS_COP0(VALUE) (MIPS_OP(16) | MIPS_RS(VALUE))
|
||||
#define MIPS_COP1(VALUE) (MIPS_OP(17) | MIPS_RS(VALUE))
|
||||
#define MIPS_COP1BC(VALUE) (MIPS_COP1(8) | MIPS_RT(VALUE))
|
||||
#define MIPS_COP1S(VALUE) (MIPS_COP1(16) | MIPS_FUNC(VALUE))
|
||||
#define MIPS_COP1W(VALUE) (MIPS_COP1(20) | MIPS_FUNC(VALUE))
|
||||
|
||||
#define MIPS_VFPUSIZE(VALUE) ( (((VALUE) & 1) << 7) | (((VALUE) & 2) << 14) )
|
||||
#define MIPS_VFPUFUNC(VALUE) BITFIELD(23, 3, (VALUE))
|
||||
#define MIPS_COP2(VALUE) (MIPS_OP(18) | MIPS_RS(VALUE))
|
||||
#define MIPS_COP2BC(VALUE) (MIPS_COP2(8) | MIPS_RT(VALUE))
|
||||
#define MIPS_VFPU0(VALUE) (MIPS_OP(24) | MIPS_VFPUFUNC(VALUE))
|
||||
#define MIPS_VFPU1(VALUE) (MIPS_OP(25) | MIPS_VFPUFUNC(VALUE))
|
||||
#define MIPS_VFPU3(VALUE) (MIPS_OP(27) | MIPS_VFPUFUNC(VALUE))
|
||||
#define MIPS_SPECIAL3(VALUE) (MIPS_OP(31) | MIPS_FUNC(VALUE))
|
||||
#define MIPS_ALLEGREX0(VALUE) (MIPS_SPECIAL3(32) | MIPS_SECFUNC(VALUE))
|
||||
#define MIPS_VFPU4(VALUE) (MIPS_OP(52) | MIPS_RS(VALUE))
|
||||
#define MIPS_VFPU4_11(VALUE) (MIPS_VFPU4(0) | MIPS_RT(VALUE))
|
||||
#define MIPS_VFPU4_12(VALUE) (MIPS_VFPU4(1) | MIPS_RT(VALUE))
|
||||
#define MIPS_VFPU4_13(VALUE) (MIPS_VFPU4(2) | MIPS_RT(VALUE))
|
||||
#define MIPS_VFPU5(VALUE) (MIPS_OP(55) | MIPS_VFPUFUNC(VALUE))
|
||||
|
||||
#define MIPS_VFPU_ALLSIZES(name, args, code, flags) \
|
||||
{ name ".s", args, code | MIPS_VFPUSIZE(0), flags }, \
|
||||
{ name ".p", args, code | MIPS_VFPUSIZE(1), flags }, \
|
||||
{ name ".t", args, code | MIPS_VFPUSIZE(2), flags }, \
|
||||
{ name ".q", args, code | MIPS_VFPUSIZE(3), flags }
|
||||
|
||||
extern const tMipsRegister MipsRegister[];
|
||||
extern const tMipsRegister MipsFloatRegister[];
|
||||
extern const tMipsOpcode MipsOpcodes[];
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
#include "Core/MIPS/MIPSCodeUtils.h"
|
||||
#include "Core/MIPS/MIPSDebugInterface.h"
|
||||
#include "Core/MIPS/MIPSAsm.h"
|
||||
#include "Core/MIPS/MIPSTables.h"
|
||||
#include "Core/MemMap.h"
|
||||
#include "Core/Core.h"
|
||||
#include "Core/CoreTiming.h"
|
||||
@ -130,7 +131,6 @@ bool TestJit() {
|
||||
*p++ = 0xD03C0000 | (1 << 7) | (1 << 15) | (7 << 8);
|
||||
*/
|
||||
for (size_t j = 0; j < ARRAY_SIZE(lines); ++j) {
|
||||
if (i == 0) printf("%s\n", lines[j]);
|
||||
if (!MIPSAsm::MipsAssembleOpcode(lines[j], currentDebugMIPS, addr, *p++)) {
|
||||
printf("ERROR: %s\n", MIPSAsm::GetAssembleError());
|
||||
compileSuccess = false;
|
||||
@ -142,6 +142,15 @@ bool TestJit() {
|
||||
*p++ = MIPS_MAKE_SYSCALL("UnitTestFakeSyscalls", "UnitTestTerminator");
|
||||
*p++ = MIPS_MAKE_BREAK(1);
|
||||
|
||||
// Dogfood.
|
||||
addr = currentMIPS->pc;
|
||||
for (size_t j = 0; j < ARRAY_SIZE(lines); ++j) {
|
||||
char line[512];
|
||||
MIPSDisAsm(Memory::Read_Instruction(addr), addr, line, true);
|
||||
addr += 4;
|
||||
printf("%s\n", line);
|
||||
}
|
||||
|
||||
printf("\n");
|
||||
|
||||
double jit_speed, interp_speed;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user