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Add Try arm emitter I2R funcs.

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This way we can use them without giving up the regcache's immediate
optimizations.
This commit is contained in:
Unknown W. Brackets 2014-03-14 17:47:34 -07:00
parent 48fa22b7cf
commit 3a07924ad9
2 changed files with 118 additions and 44 deletions
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155
Common/ArmEmitter.cpp
View File

@ -163,11 +163,19 @@ void ARMXEmitter::MOVI2F(ARMReg dest, float val, ARMReg tempReg, bool negate)
} }
void ARMXEmitter::ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch) void ARMXEmitter::ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryADDI2R(rd, rs, val)) {
MOVI2R(scratch, val);
ADD(rd, rs, scratch);
}
}
bool ARMXEmitter::TryADDI2R(ARMReg rd, ARMReg rs, u32 val)
{ {
if (val == 0) { if (val == 0) {
if (rd != rs) if (rd != rs)
MOV(rd, rs); MOV(rd, rs);
return; return true;
} }
Operand2 op2; Operand2 op2;
bool negated; bool negated;
@ -176,6 +184,7 @@ void ARMXEmitter::ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
ADD(rd, rs, op2); ADD(rd, rs, op2);
else else
SUB(rd, rs, op2); SUB(rd, rs, op2);
return true;
} else { } else {
// Try 16-bit additions and subtractions - easy to test for. // Try 16-bit additions and subtractions - easy to test for.
// Should also try other rotations... // Should also try other rotations...
@ -183,30 +192,41 @@ void ARMXEmitter::ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
// Decompose into two additions. // Decompose into two additions.
ADD(rd, rs, Operand2((u8)(val >> 8), 12)); // rotation right by 12*2 == rotation left by 8 ADD(rd, rs, Operand2((u8)(val >> 8), 12)); // rotation right by 12*2 == rotation left by 8
ADD(rd, rd, Operand2((u8)(val), 0)); ADD(rd, rd, Operand2((u8)(val), 0));
return true;
} else if ((((u32)-(s32)val) & 0xFFFF0000) == 0) { } else if ((((u32)-(s32)val) & 0xFFFF0000) == 0) {
val = (u32)-(s32)val; val = (u32)-(s32)val;
SUB(rd, rs, Operand2((u8)(val >> 8), 12)); SUB(rd, rs, Operand2((u8)(val >> 8), 12));
SUB(rd, rd, Operand2((u8)(val), 0)); SUB(rd, rd, Operand2((u8)(val), 0));
return true;
} else { } else {
MOVI2R(scratch, val); return false;
ADD(rd, rs, scratch);
} }
} }
} }
void ARMXEmitter::ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch) void ARMXEmitter::ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryANDI2R(rd, rs, val)) {
MOVI2R(scratch, val);
AND(rd, rs, scratch);
}
}
bool ARMXEmitter::TryANDI2R(ARMReg rd, ARMReg rs, u32 val)
{ {
Operand2 op2; Operand2 op2;
bool inverse; bool inverse;
if (val == 0) { if (val == 0) {
// Avoid the ALU, may improve pipeline. // Avoid the ALU, may improve pipeline.
MOV(rd, 0); MOV(rd, 0);
return true;
} else if (TryMakeOperand2_AllowInverse(val, op2, &inverse)) { } else if (TryMakeOperand2_AllowInverse(val, op2, &inverse)) {
if (!inverse) { if (!inverse) {
AND(rd, rs, op2); AND(rd, rs, op2);
} else { } else {
BIC(rd, rs, op2); BIC(rd, rs, op2);
} }
return true;
} else { } else {
int ops = 0; int ops = 0;
for (int i = 0; i < 32; i += 2) { for (int i = 0; i < 32; i += 2) {
@ -221,31 +241,37 @@ void ARMXEmitter::ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
// The worst case is 4 (e.g. 0x55555555.) // The worst case is 4 (e.g. 0x55555555.)
#ifdef HAVE_ARMV7 #ifdef HAVE_ARMV7
if (ops > 3) { if (ops > 3) {
MOVI2R(scratch, val); return false;
AND(rd, rs, scratch); }
} else
#endif #endif
{ bool first = true;
bool first = true; for (int i = 0; i < 32; i += 2) {
for (int i = 0; i < 32; i += 2) { u8 bits = RotR(val, i) & 0xFF;
u8 bits = RotR(val, i) & 0xFF; if ((bits & 3) != 3) {
if ((bits & 3) != 3) { u8 rotation = i == 0 ? 0 : 16 - i / 2;
u8 rotation = i == 0 ? 0 : 16 - i / 2; if (first) {
if (first) { BIC(rd, rs, Operand2(~bits, rotation));
BIC(rd, rs, Operand2(~bits, rotation)); first = false;
first = false; } else {
} else { BIC(rd, rd, Operand2(~bits, rotation));
BIC(rd, rd, Operand2(~bits, rotation));
}
// Well, we took care of these other bits while we were at it.
i += 8 - 2;
} }
// Well, we took care of these other bits while we were at it.
i += 8 - 2;
} }
} }
return true;
} }
} }
void ARMXEmitter::CMPI2R(ARMReg rs, u32 val, ARMReg scratch) void ARMXEmitter::CMPI2R(ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryCMPI2R(rs, val)) {
MOVI2R(scratch, val);
CMP(rs, scratch);
}
}
bool ARMXEmitter::TryCMPI2R(ARMReg rs, u32 val)
{ {
Operand2 op2; Operand2 op2;
bool negated; bool negated;
@ -254,24 +280,40 @@ void ARMXEmitter::CMPI2R(ARMReg rs, u32 val, ARMReg scratch)
CMP(rs, op2); CMP(rs, op2);
else else
CMN(rs, op2); CMN(rs, op2);
return true;
} else { } else {
MOVI2R(scratch, val); return false;
CMP(rs, scratch);
} }
} }
void ARMXEmitter::TSTI2R(ARMReg rs, u32 val, ARMReg scratch) void ARMXEmitter::TSTI2R(ARMReg rs, u32 val, ARMReg scratch)
{ {
Operand2 op2; if (!TryTSTI2R(rs, val)) {
if (TryMakeOperand2(val, op2)) {
TST(rs, op2);
} else {
MOVI2R(scratch, val); MOVI2R(scratch, val);
TST(rs, scratch); TST(rs, scratch);
} }
} }
bool ARMXEmitter::TryTSTI2R(ARMReg rs, u32 val)
{
Operand2 op2;
if (TryMakeOperand2(val, op2)) {
TST(rs, op2);
return true;
} else {
return false;
}
}
void ARMXEmitter::ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch) void ARMXEmitter::ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryORI2R(rd, rs, val)) {
MOVI2R(scratch, val);
ORR(rd, rs, scratch);
}
}
bool ARMXEmitter::TryORI2R(ARMReg rd, ARMReg rs, u32 val)
{ {
Operand2 op2; Operand2 op2;
if (val == 0) { if (val == 0) {
@ -279,8 +321,10 @@ void ARMXEmitter::ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
if (rd != rs) { if (rd != rs) {
MOV(rd, rs); MOV(rd, rs);
} }
return true;
} else if (TryMakeOperand2(val, op2)) { } else if (TryMakeOperand2(val, op2)) {
ORR(rd, rs, op2); ORR(rd, rs, op2);
return true;
} else { } else {
int ops = 0; int ops = 0;
for (int i = 0; i < 32; i += 2) { for (int i = 0; i < 32; i += 2) {
@ -295,30 +339,53 @@ void ARMXEmitter::ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
// The worst case is 4 (e.g. 0x55555555.) But MVN can make it 2. Not sure if better. // The worst case is 4 (e.g. 0x55555555.) But MVN can make it 2. Not sure if better.
bool inversed; bool inversed;
if (TryMakeOperand2_AllowInverse(val, op2, &inversed) && ops >= 3) { if (TryMakeOperand2_AllowInverse(val, op2, &inversed) && ops >= 3) {
MVN(scratch, op2); return false;
ORR(rd, rs, scratch);
#ifdef HAVE_ARMV7 #ifdef HAVE_ARMV7
} else if (ops > 3) { } else if (ops > 3) {
MOVI2R(scratch, val); return false;
ORR(rd, rs, scratch);
#endif #endif
} else { }
bool first = true;
for (int i = 0; i < 32; i += 2) { bool first = true;
u8 bits = RotR(val, i) & 0xFF; for (int i = 0; i < 32; i += 2) {
if ((bits & 3) != 0) { u8 bits = RotR(val, i) & 0xFF;
u8 rotation = i == 0 ? 0 : 16 - i / 2; if ((bits & 3) != 0) {
if (first) { u8 rotation = i == 0 ? 0 : 16 - i / 2;
ORR(rd, rs, Operand2(bits, rotation)); if (first) {
first = false; ORR(rd, rs, Operand2(bits, rotation));
} else { first = false;
ORR(rd, rd, Operand2(bits, rotation)); } else {
} ORR(rd, rd, Operand2(bits, rotation));
// Well, we took care of these other bits while we were at it.
i += 8 - 2;
} }
// Well, we took care of these other bits while we were at it.
i += 8 - 2;
} }
} }
return true;
}
}
void ARMXEmitter::EORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryEORI2R(rd, rs, val)) {
MOVI2R(scratch, val);
EOR(rd, rs, scratch);
}
}
bool ARMXEmitter::TryEORI2R(ARMReg rd, ARMReg rs, u32 val)
{
Operand2 op2;
if (val == 0) {
if (rd != rs) {
MOV(rd, rs);
}
return true;
} else if (TryMakeOperand2(val, op2)) {
EOR(rd, rs, op2);
return true;
} else {
return false;
} }
} }

7
Common/ArmEmitter.h
View File

@ -795,10 +795,17 @@ public:
} }
void ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch); void ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
bool TryADDI2R(ARMReg rd, ARMReg rs, u32 val);
void ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch); void ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
bool TryANDI2R(ARMReg rd, ARMReg rs, u32 val);
void CMPI2R(ARMReg rs, u32 val, ARMReg scratch); void CMPI2R(ARMReg rs, u32 val, ARMReg scratch);
bool TryCMPI2R(ARMReg rs, u32 val);
void TSTI2R(ARMReg rs, u32 val, ARMReg scratch); void TSTI2R(ARMReg rs, u32 val, ARMReg scratch);
bool TryTSTI2R(ARMReg rs, u32 val);
void ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch); void ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
bool TryORI2R(ARMReg rd, ARMReg rs, u32 val);
void EORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
bool TryEORI2R(ARMReg rd, ARMReg rs, u32 val);
}; // class ARMXEmitter }; // class ARMXEmitter