From 4459b8f48322ee069396c19217060c6fa9d52da4 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Mon, 1 Sep 2014 23:13:07 -0700
Subject: [PATCH] jit: Actually jit vmtfc/vmfvc.

Sicne we have them and they are easy.
---
 Core/MIPS/ARM/ArmCompVFPU.cpp     | 19 +++++++++++++++++++
 Core/MIPS/ARM/ArmCompVFPUNEON.cpp |  4 ++++
 Core/MIPS/ARM/ArmJit.h            |  2 ++
 Core/MIPS/MIPSTables.cpp          |  4 ++--
 Core/MIPS/PPC/PpcCompVFPU.cpp     | 13 +++++++++++++
 Core/MIPS/PPC/PpcJit.h            |  1 +
 Core/MIPS/x86/CompVFPU.cpp        | 16 ++++++++++++++++
 Core/MIPS/x86/Jit.h               |  1 +
 8 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/Core/MIPS/ARM/ArmCompVFPU.cpp b/Core/MIPS/ARM/ArmCompVFPU.cpp
index f51fd6b3d..eda34c5c5 100644
--- a/Core/MIPS/ARM/ArmCompVFPU.cpp
+++ b/Core/MIPS/ARM/ArmCompVFPU.cpp
@@ -1277,6 +1277,25 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
+	void Jit::Comp_Vmfvc(MIPSOpcode op) {
+		NEON_IF_AVAILABLE(CompNEON_Vmtvc);
+		CONDITIONAL_DISABLE;
+
+		int vs = _VS;
+		int imm = op & 0xFF;
+		if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
+			fpr.MapRegV(vs);
+			if (imm - 128 == VFPU_CTRL_CC) {
+				gpr.MapReg(MIPS_REG_VFPUCC, 0);
+				VMOV(fpr.V(vs), gpr.R(MIPS_REG_VFPUCC));
+			} else {
+				ADDI2R(SCRATCHREG1, CTXREG, offsetof(MIPSState, vfpuCtrl[0]) + (imm - 128) * 4, SCRATCHREG2);
+				VLDR(fpr.V(vs), SCRATCHREG1, 0);
+			}
+			fpr.ReleaseSpillLocksAndDiscardTemps();
+		}
+	}
+
 	void Jit::Comp_Vmtvc(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vmtvc);
 		CONDITIONAL_DISABLE;
diff --git a/Core/MIPS/ARM/ArmCompVFPUNEON.cpp b/Core/MIPS/ARM/ArmCompVFPUNEON.cpp
index 4ec568a79..b3a6bec5f 100644
--- a/Core/MIPS/ARM/ArmCompVFPUNEON.cpp
+++ b/Core/MIPS/ARM/ArmCompVFPUNEON.cpp
@@ -73,6 +73,10 @@ void Jit::CompNEON_Mftv(MIPSOpcode op) {
 	DISABLE;
 }
 
+void Jit::CompNEON_Vmfvc(MIPSOpcode op) {
+	DISABLE;
+}
+
 void Jit::CompNEON_Vmtvc(MIPSOpcode op) {
 	DISABLE;
 }
diff --git a/Core/MIPS/ARM/ArmJit.h b/Core/MIPS/ARM/ArmJit.h
index 5fd96a4ef..b5f125225 100644
--- a/Core/MIPS/ARM/ArmJit.h
+++ b/Core/MIPS/ARM/ArmJit.h
@@ -110,6 +110,7 @@ public:
 	void Comp_VecDo3(MIPSOpcode op);
 	void Comp_VV2Op(MIPSOpcode op);
 	void Comp_Mftv(MIPSOpcode op);
+	void Comp_Vmfvc(MIPSOpcode op);
 	void Comp_Vmtvc(MIPSOpcode op);
 	void Comp_Vmmov(MIPSOpcode op);
 	void Comp_VScl(MIPSOpcode op);
@@ -147,6 +148,7 @@ public:
 	void CompNEON_VecDo3(MIPSOpcode op);
 	void CompNEON_VV2Op(MIPSOpcode op);
 	void CompNEON_Mftv(MIPSOpcode op);
+	void CompNEON_Vmfvc(MIPSOpcode op);
 	void CompNEON_Vmtvc(MIPSOpcode op);
 	void CompNEON_Vmmov(MIPSOpcode op);
 	void CompNEON_VScl(MIPSOpcode op);
diff --git a/Core/MIPS/MIPSTables.cpp b/Core/MIPS/MIPSTables.cpp
index d91411866..fe5e26990 100644
--- a/Core/MIPS/MIPSTables.cpp
+++ b/Core/MIPS/MIPSTables.cpp
@@ -763,9 +763,9 @@ const MIPSInstruction tableVFPU9[32] = // 110100 00010 xxxxx . ....... . .......
 
 	//16
 	// TODO: Flags may not be correct (prefixes, etc.)
-	INSTR("vmfvc", &Jit::Comp_Generic, Dis_Vmftvc, Int_Vmfvc, IN_OTHER|OUT_OTHER|IS_VFPU),
+	INSTR("vmfvc", &Jit::Comp_Vmfvc, Dis_Vmftvc, Int_Vmfvc, IN_OTHER|OUT_OTHER|IS_VFPU),
 	// TODO: Flags may not be correct (prefixes, etc.)
-	INSTR("vmtvc", &Jit::Comp_Generic, Dis_Vmftvc, Int_Vmtvc, IN_OTHER|OUT_OTHER|IS_VFPU),
+	INSTR("vmtvc", &Jit::Comp_Vmtvc, Dis_Vmftvc, Int_Vmtvc, IN_OTHER|OUT_OTHER|IS_VFPU),
 	INVALID,
 	INVALID,
 
diff --git a/Core/MIPS/PPC/PpcCompVFPU.cpp b/Core/MIPS/PPC/PpcCompVFPU.cpp
index cd9f405f6..65b530e3a 100644
--- a/Core/MIPS/PPC/PpcCompVFPU.cpp
+++ b/Core/MIPS/PPC/PpcCompVFPU.cpp
@@ -712,6 +712,19 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
+	void Jit::Comp_Vmfvc(MIPSOpcode op) {
+		CONDITIONAL_DISABLE;
+
+		int vs = _VS;
+		int imm = op & 0xFF;
+		if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
+			fpr.MapRegV(vs);
+			ADDI(SREG, CTXREG, offsetof(MIPSState, vfpuCtrl[0]) + (imm - 128) * 4);
+			LFS(fpr.V(vs), SREG, 0);
+			fpr.ReleaseSpillLocksAndDiscardTemps();
+		}
+	}
+
 	void Jit::Comp_Vmtvc(MIPSOpcode op) {
 		CONDITIONAL_DISABLE;
 
diff --git a/Core/MIPS/PPC/PpcJit.h b/Core/MIPS/PPC/PpcJit.h
index 4f88017b7..7706b1441 100644
--- a/Core/MIPS/PPC/PpcJit.h
+++ b/Core/MIPS/PPC/PpcJit.h
@@ -215,6 +215,7 @@ namespace MIPSComp
 		void Comp_VecDo3(MIPSOpcode op);
 		void Comp_VV2Op(MIPSOpcode op);
 		void Comp_Mftv(MIPSOpcode op);
+		void Comp_Vmfvc(MIPSOpcode op);
 		void Comp_Vmtvc(MIPSOpcode op);
 		void Comp_Vmmov(MIPSOpcode op);
 		void Comp_VScl(MIPSOpcode op);
diff --git a/Core/MIPS/x86/CompVFPU.cpp b/Core/MIPS/x86/CompVFPU.cpp
index bb670763c..12359aa4e 100644
--- a/Core/MIPS/x86/CompVFPU.cpp
+++ b/Core/MIPS/x86/CompVFPU.cpp
@@ -1742,6 +1742,22 @@ void Jit::Comp_Mftv(MIPSOpcode op) {
 	}
 }
 
+void Jit::Comp_Vmfvc(MIPSOpcode op) {
+	CONDITIONAL_DISABLE;
+	int vs = _VS;
+	int imm = op & 0xFF;
+	if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
+		fpr.MapRegV(vs, 0);
+		if (imm - 128 == VFPU_CTRL_CC) {
+			gpr.MapReg(MIPS_REG_VFPUCC, true, false);
+			MOVD_xmm(fpr.VX(vs), gpr.R(MIPS_REG_VFPUCC));
+		} else {
+			MOVSS(fpr.VX(vs), M(&currentMIPS->vfpuCtrl[imm - 128]));
+		}
+		fpr.ReleaseSpillLocks();
+	}
+}
+
 void Jit::Comp_Vmtvc(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	int vs = _VS;
diff --git a/Core/MIPS/x86/Jit.h b/Core/MIPS/x86/Jit.h
index 44ee34f92..385f5c4cc 100644
--- a/Core/MIPS/x86/Jit.h
+++ b/Core/MIPS/x86/Jit.h
@@ -118,6 +118,7 @@ public:
 	void Comp_VecDo3(MIPSOpcode op);
 	void Comp_VV2Op(MIPSOpcode op);
 	void Comp_Mftv(MIPSOpcode op);
+	void Comp_Vmfvc(MIPSOpcode op);
 	void Comp_Vmtvc(MIPSOpcode op);
 	void Comp_Vmmov(MIPSOpcode op);
 	void Comp_VScl(MIPSOpcode op);