From 471ddd63805663a2d130599b2fe6dddd54364f66 Mon Sep 17 00:00:00 2001
From: Sacha <xsacha@gmail.com>
Date: Tue, 26 Mar 2013 02:41:15 +1000
Subject: [PATCH] Simplify armjit.

---
 Common/ArmEmitter.cpp         | 30 +++++++++++++++++++++++++++++
 Common/ArmEmitter.h           |  2 ++
 Core/MIPS/ARM/ArmCompALU.cpp  | 36 +++--------------------------------
 Core/MIPS/ARM/ArmCompVFPU.cpp |  9 +++------
 4 files changed, 38 insertions(+), 39 deletions(-)

diff --git a/Common/ArmEmitter.cpp b/Common/ArmEmitter.cpp
index f5656144e..96665a444 100644
--- a/Common/ArmEmitter.cpp
+++ b/Common/ArmEmitter.cpp
@@ -100,6 +100,21 @@ void ARMXEmitter::MOVI2F(ARMReg dest, float val, ARMReg tempReg)
 	// Otherwise, use a literal pool and VLDR directly (+- 1020)
 }
 
+void ARMXEmitter::ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
+{
+	Operand2 op2;
+	bool negated;
+	if (TryMakeOperand2_AllowNegation(val, op2, &negated)) {
+		if (!negated)
+			ADD(rd, rs, op2);
+		else
+			SUB(rd, rs, op2);
+	} else {
+		MOVI2R(scratch, val);
+		ADD(rd, rs, scratch);
+	}
+}
+
 void ARMXEmitter::ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
 {
 	Operand2 op2;
@@ -116,6 +131,21 @@ void ARMXEmitter::ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
 	}
 }
 
+void ARMXEmitter::CMPI2R(ARMReg rs, u32 val, ARMReg scratch)
+{
+	Operand2 op2;
+	bool negated;
+	if (TryMakeOperand2_AllowNegation(val, op2, &negated)) {
+		if (!negated)
+			CMP(rs, op2);
+		else
+			CMN(rs, op2);
+	} else {
+		MOVI2R(scratch, val);
+		CMP(rs, scratch);
+	}
+}
+
 void ARMXEmitter::ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
 {
 	Operand2 op2;
diff --git a/Common/ArmEmitter.h b/Common/ArmEmitter.h
index f6b92705a..144e3d76f 100644
--- a/Common/ArmEmitter.h
+++ b/Common/ArmEmitter.h
@@ -558,7 +558,9 @@ public:
 	void MOVI2R(ARMReg reg, u32 val, bool optimize = true);
 	void MOVI2F(ARMReg dest, float val, ARMReg tempReg);
 
+	void ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
 	void ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
+	void CMPI2R(ARMReg rs, u32 val, ARMReg scratch);
 	void ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
 
 
diff --git a/Core/MIPS/ARM/ArmCompALU.cpp b/Core/MIPS/ARM/ArmCompALU.cpp
index 20a4f2744..d42fe1785 100644
--- a/Core/MIPS/ARM/ArmCompALU.cpp
+++ b/Core/MIPS/ARM/ArmCompALU.cpp
@@ -84,17 +84,7 @@ namespace MIPSComp
 					gpr.SetImm(rt, gpr.GetImm(rs) + simm);
 				} else {
 					gpr.MapDirtyIn(rt, rs);
-					Operand2 op2;
-					bool negated;
-					if (TryMakeOperand2_AllowNegation(simm, op2, &negated)) {
-						if (!negated)
-							ADD(gpr.R(rt), gpr.R(rs), op2);
-						else
-							SUB(gpr.R(rt), gpr.R(rs), op2);
-					} else {
-						MOVI2R(R0, (u32)simm);
-						ADD(gpr.R(rt), gpr.R(rs), R0);
-					}
+					ADDI2R(gpr.R(rt), gpr.R(rs), simm, R0);
 				}
 				break;
 			}
@@ -106,17 +96,7 @@ namespace MIPSComp
 		case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
 			{
 				gpr.MapDirtyIn(rt, rs);
-				Operand2 op2;
-				bool negated;
-				if (TryMakeOperand2_AllowNegation(simm, op2, &negated)) {
-					if (!negated)
-						CMP(gpr.R(rs), op2);
-					else
-						CMN(gpr.R(rs), op2);
-				} else {
-					MOVI2R(R0, simm);
-					CMP(gpr.R(rs), R0);
-				}
+				CMPI2R(gpr.R(rs), simm, R0);
 				SetCC(CC_LT);
 				MOVI2R(gpr.R(rt), 1);
 				SetCC(CC_GE);
@@ -128,17 +108,7 @@ namespace MIPSComp
 		case 11: // R(rt) = R(rs) < uimm; break; //sltiu
 			{
 				gpr.MapDirtyIn(rt, rs);
-				Operand2 op2;
-				bool negated;
-				if (TryMakeOperand2_AllowNegation(suimm, op2, &negated)) {
-					if (!negated)
-						CMP(gpr.R(rs), op2);
-					else
-						CMN(gpr.R(rs), op2);
-				} else {
-					MOVI2R(R0, suimm);
-					CMP(gpr.R(rs), R0);
-				}
+				CMPI2R(gpr.R(rs), suimm, R0);
 				SetCC(CC_LO);
 				MOVI2R(gpr.R(rt), 1);
 				SetCC(CC_HS);
diff --git a/Core/MIPS/ARM/ArmCompVFPU.cpp b/Core/MIPS/ARM/ArmCompVFPU.cpp
index db9764d9b..0a70ef184 100644
--- a/Core/MIPS/ARM/ArmCompVFPU.cpp
+++ b/Core/MIPS/ARM/ArmCompVFPU.cpp
@@ -582,13 +582,11 @@ namespace MIPSComp
 				DISABLE;
 				break;
 			case 16: // d[i] = 1.0f / s[i]; break; //vrcp
-				MOVI2R(R0, 0x3F800000);  // 1.0f
-				VMOV(S0, R0);
+				MOVI2F(S0, 1.0f, R0);
 				VDIV(tempxregs[i], S0, fpr.V(sregs[i]));
 				break;
 			case 17: // d[i] = 1.0f / sqrtf(s[i]); break; //vrsq
-				MOVI2R(R0, 0x3F800000);  // 1.0f
-				VMOV(S0, R0);
+				MOVI2F(S0, 1.0f, R0);
 				VSQRT(S1, fpr.V(sregs[i]));
 				VDIV(tempxregs[i], S0, S1);
 				break;
@@ -612,8 +610,7 @@ namespace MIPSComp
 				DISABLE;
 				break;
 			case 24: // d[i] = -1.0f / s[i]; break; // vnrcp
-				MOVI2R(R0, 0x80000000 | 0x3F800000);  // -1.0f
-				VMOV(S0, R0);
+				MOVI2F(S0, -1.0f, R0);
 				VDIV(tempxregs[i], S0, fpr.V(sregs[i]));
 				break;
 			case 26: // d[i] = -sinf((float)M_PI_2 * s[i]); break; // vnsin