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Minor fixes

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This commit is contained in:
Henrik Rydgard 2014-12-08 00:18:13 +01:00
parent 8c128508a5
commit 50bb3e1e05
6 changed files with 15 additions and 8 deletions
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2
Core/MIPS/ARM/ArmJit.cpp
View File

@ -48,7 +48,7 @@ void DisassembleArm(const u8 *data, int size) {
int reg0 = (inst & 0x0000F000) >> 12;
int reg1 = (next & 0x0000F000) >> 12;
if (reg0 == reg1) {
sprintf(temp, "%08x MOV32? %s, %04x%04x", (u32)inst, ArmRegName(reg0), hi, low);
sprintf(temp, "%08x MOV32 %s, %04x%04x", (u32)inst, ArmRegName(reg0), hi, low);
ILOG("A: %s", temp);
i += 4;
continue;

6
Core/MIPS/ARM/ArmRegCacheFPU.cpp
View File

@ -758,7 +758,7 @@ int ArmRegCacheFPU::QGetFreeQuad(int start, int count, const char *reason) {
ERROR_LOG(JIT, "Failed finding a free quad. Things will now go haywire!");
return -1;
} else {
INFO_LOG(JIT, "No register found in %i and the next %i, kicked out %i (%s)", start, count, bestQuad, reason ? reason : "no reason");
INFO_LOG(JIT, "No register found in %i and the next %i, kicked out #%i (%s)", start, count, bestQuad, reason ? reason : "no reason");
QFlush(bestQuad);
return bestQuad;
}
@ -866,7 +866,7 @@ ARMReg ArmRegCacheFPU::QMapReg(int vreg, VectorSize sz, int flags) {
return (ARMReg)(Q0 + q);
} else {
INFO_LOG(JIT, "Quad out of range %i (count = %i), needs moving. For now we flush.", start, count);
INFO_LOG(JIT, "Quad already mapped at %i which is out of requested range [%i-%i) (count = %i), needs moving. For now we flush.", q, start, start+count, count);
quadsToFlush.push_back(q);
continue;
}
@ -912,7 +912,7 @@ ARMReg ArmRegCacheFPU::QMapReg(int vreg, VectorSize sz, int flags) {
qr[quad].sz = sz;
qr[quad].mipsVec = vreg;
if (!(flags & MAP_NOINIT)) {
if ((flags & MAP_NOINIT) != MAP_NOINIT) {
// Okay, now we will try to load the whole thing in one go. This is possible
// if it's a row and easy if it's a single.
// Rows are rare, columns are common - but thanks to our register reordering,

1
Core/MIPS/JitCommon/JitCommon.cpp
View File

@ -49,7 +49,6 @@ std::vector<std::string> DisassembleArm2(const u8 *data, int size) {
int reg1 = (next & 0x0000F000) >> 12;
if (reg0 == reg1) {
snprintf(temp, sizeof(temp), "MOV32 %s, %04x%04x", ArmRegName(reg0), hi, low);
// sprintf(temp, "%08x MOV32? %s, %04x%04x", (u32)inst, ArmRegName(reg0), hi, low);
lines.push_back(temp);
i += 4;
continue;

2
ext/armips

@ -1 +1 @@
Subproject commit b261c12669437574c8ac6e2a6dc61bce70a2cae4
Subproject commit 6bfecc918d6b42302966d8598c20dd37e4c0247e

4
ext/disarm.cpp
View File

@ -538,6 +538,7 @@ static bool DisasmNeonVecScalar(uint32_t op, char *text) {
break;
case 0x14:
case 0x1C:
case 0x1E: // Hmmm.. Should look this up :P
opname = "VMLA";
break;
}
@ -616,6 +617,9 @@ static bool DisasmNeonF2F3(uint32_t op, char *text) {
opname = "EOR";
includeSuffix = false;
break;
case 0xd0:
opname = "PADD";
break;
default:
opname = "MUL";
}

8
unittest/TestArmEmitter.cpp
View File

@ -100,8 +100,12 @@ bool TestArmEmitter() {
emitter.VBIC_imm(I_32, R0, VIMM___x___x, 0xF3);
emitter.VMVN_imm(I_32, R0, VIMM___x___x, 0xF3);
emitter.VPADD(F_32, D0, D0, D0);
RET(CheckLast(emitter, "f3000d00 VPADD.f32 d0, d0, d0"));
emitter.VMOV(Q14, Q2);
emitter.VMLA_scalar(F_32, Q8, Q13, DScalar(D8, 1));
RET(CheckLast(emitter, "f3ea01e8 VMLA.f32 q8, q13, d8[1]"));
emitter.VMOV(S9, R3);
RET(CheckLast(emitter, "ee043a90 VMOV s9, r3"));
emitter.VMOV(R9, S3);
@ -206,8 +210,8 @@ bool TestArmEmitter() {
int R001 = GetRowName(0, M_4x4, 1, 0);
int R002 = GetRowName(0, M_4x4, 2, 0);
int R003 = GetRowName(0, M_4x4, 3, 0);
printf("Col 000: %s\n", GetVectorNotation(C000, V_Quad));
printf("Row 000: %s\n", GetVectorNotation(R000, V_Quad));
printf("Col 010: %s\n", GetVectorNotation(C010, V_Quad));
printf("Row 003: %s\n", GetVectorNotation(R003, V_Quad));
MIPSAnalyst::AnalysisResults results;
memset(&results, 0, sizeof(results));