mirror of
https://github.com/libretro/ppsspp.git
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Merge pull request #3372 from unknownbrackets/mips-minor
Typesafety in MIPS processing, clean up analysis (not using it yet)
This commit is contained in:
Henrik Rydgård
commit
517b18ee58
@ -46,7 +46,7 @@ static u32 ComputeHash(u32 start, u32 size)
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{
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u32 hash=0;
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for (unsigned int i=start; i<start+size; i+=4)
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hash = hasher(hash, Memory::Read_Instruction(i));
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hash = hasher(hash, Memory::Read_Instruction(i).encoding);
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return hash;
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}
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@ -546,7 +546,7 @@ void SymbolMap::CompileFuncSignaturesFile(const char *filename) const
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int size = entry.size;
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if (size >= 16 && entry.type == ST_FUNCTION)
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{
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u32 inst = Memory::Read_Instruction(entry.vaddress); //try to make a bigger number of different vals sometime
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u32 inst = Memory::Read_Instruction(entry.vaddress).encoding; //try to make a bigger number of different vals sometime
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if (inst != 0)
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{
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char temp[64];
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@ -633,7 +633,7 @@ void SymbolMap::UseFuncSignaturesFile(const char *filename, u32 maxAddress)
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sprintf(temp,"Scanning: %08x",addr);
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lastAddr=addr;
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}
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u32 inst = Memory::Read_Instruction(addr);
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u32 inst = Memory::Read_Instruction(addr).encoding;
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if (!inst)
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continue;
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@ -68,7 +68,7 @@ void ElfReader::LoadRelocations(Elf32_Rel *rels, int numRelocs)
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addr += segmentVAddr[readwrite];
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u32 op = Memory::ReadUnchecked_U32(addr);
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u32 op = Memory::Read_Instruction(addr).encoding;
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const bool log = false;
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//log=true;
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@ -145,7 +145,7 @@ void ElfReader::LoadRelocations(Elf32_Rel *rels, int numRelocs)
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case R_MIPS_16:
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{
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char temp[256];
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MIPSDisAsm(op, 0, temp);
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MIPSDisAsm(MIPSOpcode(op), 0, temp);
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ERROR_LOG_REPORT(LOADER, "WARNING: Unsupported R_MIPS_16 reloc @ %08x : %s", addr, temp);
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}
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break;
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@ -157,7 +157,7 @@ void ElfReader::LoadRelocations(Elf32_Rel *rels, int numRelocs)
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default:
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{
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char temp[256];
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MIPSDisAsm(op, 0, temp);
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MIPSDisAsm(MIPSOpcode(op), 0, temp);
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ERROR_LOG_REPORT(LOADER,"ARGH IT'S AN UNKNOWN RELOCATION!!!!!!!! %08x, type=%d : %s", addr, type, temp);
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}
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break;
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@ -456,7 +456,7 @@ inline void updateSyscallStats(int modulenum, int funcnum, double total)
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}
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}
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void CallSyscall(u32 op)
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void CallSyscall(MIPSOpcode op)
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{
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double start = 0.0; // need to initialize to fix the race condition where g_Config.bShowDebugStats is enabled in the middle of this func.
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if (g_Config.bShowDebugStats)
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@ -114,6 +114,6 @@ void HLEShutdown();
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u32 GetNibByName(const char *module, const char *function);
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u32 GetSyscallOp(const char *module, u32 nib);
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void WriteSyscall(const char *module, u32 nib, u32 address);
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void CallSyscall(u32 op);
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void CallSyscall(MIPSOpcode op);
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void ResolveSyscall(const char *moduleName, u32 nib, u32 address);
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@ -305,7 +305,7 @@ void WriteVarSymbol(u32 exportAddress, u32 relocAddress, u8 type)
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static std::vector<HI16RelocInfo> lastHI16Relocs;
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static bool lastHI16Processed = true;
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u32 relocData = Memory::Read_Instruction(relocAddress);
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u32 relocData = Memory::Read_Instruction(relocAddress).encoding;
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switch (type)
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{
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@ -341,7 +341,7 @@ void WriteVarSymbol(u32 exportAddress, u32 relocAddress, u8 type)
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// The R_MIPS_LO16 and R_MIPS_HI16 will often be *different* relocAddress values.
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HI16RelocInfo reloc;
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reloc.addr = relocAddress;
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reloc.data = Memory::Read_Instruction(relocAddress);
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reloc.data = Memory::Read_Instruction(relocAddress).encoding;
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lastHI16Relocs.push_back(reloc);
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lastHI16Processed = false;
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break;
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@ -140,7 +140,7 @@ struct MsgPipe : public KernelObject
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void AddWaitingThread(std::vector<MsgPipeWaitingThread> &list, SceUID id, u32 addr, u32 size, int waitMode, u32 transferredBytesAddr)
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{
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MsgPipeWaitingThread thread = { id, addr, size, size, waitMode, transferredBytesAddr };
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MsgPipeWaitingThread thread = { id, addr, size, size, waitMode, { transferredBytesAddr } };
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// Start out with 0 transferred bytes while waiting.
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// TODO: for receive, it might be a different (partial) number.
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if (thread.transferredBytes.IsValid())
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@ -442,7 +442,7 @@ int __KernelSendMsgPipe(MsgPipe *m, u32 sendBufAddr, u32 sendSize, int waitMode,
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if (waitMode != SCE_KERNEL_MPW_ASAP && waitMode != SCE_KERNEL_MPW_FULL)
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{
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ERROR_LOG(HLE, "__KernelSendMsgPipe(%d): invalid wait mode", uid, waitMode);
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ERROR_LOG(HLE, "__KernelSendMsgPipe(%d): invalid wait mode %d", uid, waitMode);
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return SCE_KERNEL_ERROR_ILLEGAL_MODE;
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}
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@ -605,7 +605,7 @@ int __KernelReceiveMsgPipe(MsgPipe *m, u32 receiveBufAddr, u32 receiveSize, int
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if (waitMode != SCE_KERNEL_MPW_ASAP && waitMode != SCE_KERNEL_MPW_FULL)
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{
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ERROR_LOG(HLE, "__KernelReceiveMsgPipe(%d): invalid wait mode", uid, waitMode);
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ERROR_LOG(HLE, "__KernelReceiveMsgPipe(%d): invalid wait mode %d", uid, waitMode);
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return SCE_KERNEL_ERROR_ILLEGAL_MODE;
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}
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@ -61,7 +61,7 @@ namespace MIPSComp
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}
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}
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void Jit::Comp_IType(u32 op)
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void Jit::Comp_IType(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension
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@ -127,7 +127,7 @@ namespace MIPSComp
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}
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}
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void Jit::Comp_RType2(u32 op)
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void Jit::Comp_RType2(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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int rs = _RS;
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@ -180,7 +180,7 @@ namespace MIPSComp
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}
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}
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void Jit::Comp_RType3(u32 op)
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void Jit::Comp_RType3(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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int rt = _RT;
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@ -325,7 +325,7 @@ namespace MIPSComp
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}
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}
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void Jit::CompShiftImm(u32 op, ArmGen::ShiftType shiftType)
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void Jit::CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType)
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{
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int rd = _RD;
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int rt = _RT;
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@ -335,7 +335,7 @@ namespace MIPSComp
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MOV(gpr.R(rd), Operand2(gpr.R(rt), shiftType, sa));
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}
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void Jit::CompShiftVar(u32 op, ArmGen::ShiftType shiftType)
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void Jit::CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType)
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{
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int rd = _RD;
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int rt = _RT;
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@ -352,7 +352,7 @@ namespace MIPSComp
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MOV(gpr.R(rd), Operand2(gpr.R(rt), shiftType, R0));
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}
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void Jit::Comp_ShiftType(u32 op)
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void Jit::Comp_ShiftType(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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int rs = _RS;
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@ -379,7 +379,7 @@ namespace MIPSComp
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}
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}
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void Jit::Comp_Special3(u32 op)
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void Jit::Comp_Special3(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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@ -447,7 +447,7 @@ namespace MIPSComp
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}
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}
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void Jit::Comp_Allegrex(u32 op)
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void Jit::Comp_Allegrex(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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int rt = _RT;
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@ -505,7 +505,7 @@ namespace MIPSComp
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}
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}
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void Jit::Comp_Allegrex2(u32 op)
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void Jit::Comp_Allegrex2(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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int rt = _RT;
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@ -538,7 +538,7 @@ namespace MIPSComp
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}
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}
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void Jit::Comp_MulDivType(u32 op)
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void Jit::Comp_MulDivType(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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int rt = _RT;
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@ -53,7 +53,7 @@ using namespace MIPSAnalyst;
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namespace MIPSComp
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{
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void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
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void Jit::BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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@ -64,7 +64,7 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
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int rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC+4);
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC+4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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@ -113,7 +113,7 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
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}
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void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely)
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void Jit::BranchRSZeroComp(MIPSOpcode op, ArmGen::CCFlags cc, bool andLink, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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@ -123,7 +123,7 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely
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int rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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@ -164,7 +164,7 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely
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}
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void Jit::Comp_RelBranch(u32 op)
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void Jit::Comp_RelBranch(MIPSOpcode op)
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{
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// The CC flags here should be opposite of the actual branch becuase they skip the branching action.
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switch (op>>26)
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@ -187,7 +187,7 @@ void Jit::Comp_RelBranch(u32 op)
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}
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}
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void Jit::Comp_RelBranchRI(u32 op)
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void Jit::Comp_RelBranchRI(MIPSOpcode op)
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{
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switch ((op >> 16) & 0x1F)
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{
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@ -206,7 +206,7 @@ void Jit::Comp_RelBranchRI(u32 op)
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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void Jit::BranchFPFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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@ -215,7 +215,7 @@ void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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int offset = _IMM16 << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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@ -249,7 +249,7 @@ void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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js.compiling = false;
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}
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void Jit::Comp_FPUBranch(u32 op)
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void Jit::Comp_FPUBranch(MIPSOpcode op)
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{
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switch((op >> 16) & 0x1f)
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{
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@ -264,7 +264,7 @@ void Jit::Comp_FPUBranch(u32 op)
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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void Jit::BranchVFPUFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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@ -273,7 +273,7 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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int offset = _IMM16 << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)
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// The behavior is undefined - the CPU may take the second branch even if the first one passes.
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@ -321,7 +321,7 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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js.compiling = false;
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}
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void Jit::Comp_VBranch(u32 op)
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void Jit::Comp_VBranch(MIPSOpcode op)
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{
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switch ((op >> 16) & 3)
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{
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@ -332,7 +332,7 @@ void Jit::Comp_VBranch(u32 op)
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}
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}
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void Jit::Comp_Jump(u32 op)
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void Jit::Comp_Jump(MIPSOpcode op)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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@ -364,7 +364,7 @@ void Jit::Comp_Jump(u32 op)
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js.compiling = false;
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}
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void Jit::Comp_JumpReg(u32 op)
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void Jit::Comp_JumpReg(MIPSOpcode op)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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@ -372,7 +372,7 @@ void Jit::Comp_JumpReg(u32 op)
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}
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int rs = _RS;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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@ -413,7 +413,7 @@ void Jit::Comp_JumpReg(u32 op)
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}
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void Jit::Comp_Syscall(u32 op)
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void Jit::Comp_Syscall(MIPSOpcode op)
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{
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FlushAll();
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@ -428,7 +428,7 @@ void Jit::Comp_Syscall(u32 op)
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QuickCallFunction(R1, (void *)GetFunc("FakeSysCalls", NID_IDLE)->func);
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else
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{
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MOVI2R(R0, op);
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MOVI2R(R0, op.encoding);
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QuickCallFunction(R1, (void *)&CallSyscall);
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}
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RestoreDowncount();
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@ -437,7 +437,7 @@ void Jit::Comp_Syscall(u32 op)
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js.compiling = false;
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}
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void Jit::Comp_Break(u32 op)
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void Jit::Comp_Break(MIPSOpcode op)
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{
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Comp_Generic(op);
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WriteSyscallExit();
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@ -40,7 +40,7 @@
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namespace MIPSComp
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{
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void Jit::Comp_FPU3op(u32 op)
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void Jit::Comp_FPU3op(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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@ -54,7 +54,7 @@ void Jit::Comp_FPU3op(u32 op)
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case 0: VADD(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) + F(ft); //add
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case 1: VSUB(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) - F(ft); //sub
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case 2: { //F(fd) = F(fs) * F(ft); //mul
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u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
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MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Optimization possible if destination is the same
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if (fd == (int)((nextOp>>6) & 0x1F)) {
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// VMUL + VNEG -> VNMUL
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@ -78,7 +78,7 @@ void Jit::Comp_FPU3op(u32 op)
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extern int logBlocks;
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void Jit::Comp_FPULS(u32 op)
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void Jit::Comp_FPULS(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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@ -167,7 +167,7 @@ void Jit::Comp_FPULS(u32 op)
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}
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}
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|
||||
void Jit::Comp_FPUComp(u32 op) {
|
||||
void Jit::Comp_FPUComp(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
int opc = op & 0xF;
|
||||
if (opc >= 8) opc -= 8; // alias
|
||||
@ -233,7 +233,7 @@ void Jit::Comp_FPUComp(u32 op) {
|
||||
STR(R0, CTXREG, offsetof(MIPSState, fpcond));
|
||||
}
|
||||
|
||||
void Jit::Comp_FPU2op(u32 op)
|
||||
void Jit::Comp_FPU2op(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
@ -307,7 +307,7 @@ void Jit::Comp_FPU2op(u32 op)
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_mxc1(u32 op)
|
||||
void Jit::Comp_mxc1(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
|
||||
@ -121,7 +121,7 @@ namespace MIPSComp
|
||||
SetCC(CC_GT);
|
||||
}
|
||||
|
||||
void Jit::Comp_ITypeMem(u32 op)
|
||||
void Jit::Comp_ITypeMem(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int offset = (signed short)(op&0xFFFF);
|
||||
@ -194,13 +194,13 @@ namespace MIPSComp
|
||||
if (!js.inDelaySlot) {
|
||||
// Optimisation: Combine to single unaligned load/store
|
||||
bool isLeft = (o == 34 || o == 42);
|
||||
u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
// Find a matching shift in opposite direction with opposite offset.
|
||||
if (nextOp == (isLeft ? (op + (4<<26) - 3)
|
||||
: (op - (4<<26) + 3)))
|
||||
if (nextOp == (isLeft ? (op.encoding + (4<<26) - 3)
|
||||
: (op.encoding - (4<<26) + 3)))
|
||||
{
|
||||
EatInstruction(nextOp);
|
||||
nextOp = ((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x03FFFFFF); //lw, sw
|
||||
nextOp = MIPSOpcode(((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x03FFFFFF)); //lw, sw
|
||||
Comp_ITypeMem(nextOp);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -73,7 +73,7 @@ namespace MIPSComp
|
||||
return IsOverlapSafeAllowS(dreg, di, sn, sregs, tn, tregs) && sregs[di] != dreg;
|
||||
}
|
||||
|
||||
void Jit::Comp_VPFX(u32 op)
|
||||
void Jit::Comp_VPFX(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int data = op & 0xFFFFF;
|
||||
@ -231,7 +231,7 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_SV(u32 op) {
|
||||
void Jit::Comp_SV(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
s32 imm = (signed short)(op&0xFFFC);
|
||||
@ -321,7 +321,7 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_SVQ(u32 op)
|
||||
void Jit::Comp_SVQ(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
@ -433,7 +433,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_VVectorInit(u32 op)
|
||||
void Jit::Comp_VVectorInit(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
@ -470,7 +470,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_VIdt(u32 op) {
|
||||
void Jit::Comp_VIdt(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE
|
||||
|
||||
if (js.HasUnknownPrefix() || disablePrefixes) {
|
||||
@ -507,7 +507,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_VMatrixInit(u32 op)
|
||||
void Jit::Comp_VMatrixInit(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
@ -555,7 +555,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_VDot(u32 op) {
|
||||
void Jit::Comp_VDot(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
if (js.HasUnknownPrefix() || disablePrefixes) {
|
||||
DISABLE;
|
||||
@ -592,7 +592,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vhoriz(u32 op) {
|
||||
void Jit::Comp_Vhoriz(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
|
||||
switch ((op >> 16) & 31) {
|
||||
@ -603,12 +603,12 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_VHdp(u32 op) {
|
||||
void Jit::Comp_VHdp(MIPSOpcode op) {
|
||||
// Similar to vdot
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_VecDo3(u32 op) {
|
||||
void Jit::Comp_VecDo3(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix() || disablePrefixes) {
|
||||
@ -723,7 +723,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_VV2Op(u32 op) {
|
||||
void Jit::Comp_VV2Op(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix() || disablePrefixes) {
|
||||
@ -849,7 +849,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vi2f(u32 op) {
|
||||
void Jit::Comp_Vi2f(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix() || disablePrefixes)
|
||||
@ -895,7 +895,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vf2i(u32 op) {
|
||||
void Jit::Comp_Vf2i(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
DISABLE;
|
||||
|
||||
@ -963,7 +963,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Mftv(u32 op)
|
||||
void Jit::Comp_Mftv(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
@ -1024,7 +1024,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vmtvc(u32 op) {
|
||||
void Jit::Comp_Vmtvc(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
int vs = _VS;
|
||||
@ -1045,7 +1045,7 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_Vmmov(u32 op) {
|
||||
void Jit::Comp_Vmmov(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
// TODO: This probably ignores prefixes?
|
||||
@ -1086,7 +1086,7 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_VScl(u32 op) {
|
||||
void Jit::Comp_VScl(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix() || disablePrefixes) {
|
||||
@ -1135,7 +1135,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vmmul(u32 op) {
|
||||
void Jit::Comp_Vmmul(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
// TODO: This probably ignores prefixes?
|
||||
@ -1177,11 +1177,11 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_Vmscl(u32 op) {
|
||||
void Jit::Comp_Vmscl(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_Vtfm(u32 op) {
|
||||
void Jit::Comp_Vtfm(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
// TODO: This probably ignores prefixes? Or maybe uses D?
|
||||
@ -1241,23 +1241,23 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_VCrs(u32 op) {
|
||||
void Jit::Comp_VCrs(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_VDet(u32 op) {
|
||||
void Jit::Comp_VDet(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_Vi2x(u32 op) {
|
||||
void Jit::Comp_Vi2x(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_Vx2i(u32 op) {
|
||||
void Jit::Comp_Vx2i(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_VCrossQuat(u32 op) {
|
||||
void Jit::Comp_VCrossQuat(MIPSOpcode op) {
|
||||
// This op does not support prefixes.
|
||||
if (js.HasUnknownPrefix() || disablePrefixes)
|
||||
DISABLE;
|
||||
@ -1303,7 +1303,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vcmp(u32 op) {
|
||||
void Jit::Comp_Vcmp(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix() || disablePrefixes)
|
||||
@ -1441,7 +1441,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vcmov(u32 op) {
|
||||
void Jit::Comp_Vcmov(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix() || disablePrefixes)
|
||||
@ -1489,7 +1489,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Viim(u32 op) {
|
||||
void Jit::Comp_Viim(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
u8 dreg;
|
||||
@ -1503,7 +1503,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vfim(u32 op) {
|
||||
void Jit::Comp_Vfim(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix() || disablePrefixes) {
|
||||
@ -1523,7 +1523,7 @@ namespace MIPSComp
|
||||
fpr.ReleaseSpillLocksAndDiscardTemps();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vcst(u32 op) {
|
||||
void Jit::Comp_Vcst(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix() || disablePrefixes) {
|
||||
@ -1572,7 +1572,7 @@ namespace MIPSComp
|
||||
}
|
||||
|
||||
// Very heavily used by FF:CC
|
||||
void Jit::Comp_VRot(u32 op) {
|
||||
void Jit::Comp_VRot(MIPSOpcode op) {
|
||||
// Not sure about the ABI so I disable on non-Android.
|
||||
#if !defined(ARMV7) || !defined(ANDROID)
|
||||
DISABLE;
|
||||
|
||||
@ -126,13 +126,13 @@ void Jit::ClearCacheAt(u32 em_address)
|
||||
|
||||
void Jit::CompileAt(u32 addr)
|
||||
{
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
MIPSCompileOp(op);
|
||||
}
|
||||
|
||||
void Jit::EatInstruction(u32 op)
|
||||
void Jit::EatInstruction(MIPSOpcode op)
|
||||
{
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
_dbg_assert_msg_(JIT, !(info & DELAYSLOT), "Never eat a branch op.");
|
||||
_dbg_assert_msg_(JIT, !js.inDelaySlot, "Never eat an instruction inside a delayslot.");
|
||||
|
||||
@ -149,7 +149,7 @@ void Jit::CompileDelaySlot(int flags)
|
||||
MRS(R8); // Save flags register. R8 is preserved through function calls and is not allocated.
|
||||
|
||||
js.inDelaySlot = true;
|
||||
u32 op = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode op = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSCompileOp(op);
|
||||
js.inDelaySlot = false;
|
||||
|
||||
@ -224,7 +224,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
|
||||
{
|
||||
gpr.SetCompilerPC(js.compilerPC); // Let it know for log messages
|
||||
fpr.SetCompilerPC(js.compilerPC);
|
||||
u32 inst = Memory::Read_Instruction(js.compilerPC);
|
||||
MIPSOpcode inst = Memory::Read_Instruction(js.compilerPC);
|
||||
js.downcountAmount += MIPSGetInstructionCycleEstimate(inst);
|
||||
|
||||
MIPSCompileOp(inst);
|
||||
@ -266,13 +266,13 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
|
||||
return b->normalEntry;
|
||||
}
|
||||
|
||||
void Jit::Comp_RunBlock(u32 op)
|
||||
void Jit::Comp_RunBlock(MIPSOpcode op)
|
||||
{
|
||||
// This shouldn't be necessary, the dispatcher should catch us before we get here.
|
||||
ERROR_LOG(DYNA_REC, "Comp_RunBlock should never be reached!");
|
||||
}
|
||||
|
||||
void Jit::Comp_Generic(u32 op)
|
||||
void Jit::Comp_Generic(MIPSOpcode op)
|
||||
{
|
||||
FlushAll();
|
||||
MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
|
||||
@ -281,12 +281,12 @@ void Jit::Comp_Generic(u32 op)
|
||||
SaveDowncount();
|
||||
MOVI2R(R0, js.compilerPC);
|
||||
MovToPC(R0);
|
||||
MOVI2R(R0, op);
|
||||
MOVI2R(R0, op.encoding);
|
||||
QuickCallFunction(R1, (void *)func);
|
||||
RestoreDowncount();
|
||||
}
|
||||
|
||||
const int info = MIPSGetInfo(op);
|
||||
const MIPSInfo info = MIPSGetInfo(op);
|
||||
if ((info & IS_VFPU) != 0 && (info & VFPU_NO_PREFIX) == 0)
|
||||
{
|
||||
// If it does eat them, it'll happen in MIPSCompileOp().
|
||||
@ -383,7 +383,7 @@ void Jit::WriteSyscallExit()
|
||||
B((const void *)dispatcherCheckCoreState);
|
||||
}
|
||||
|
||||
void Jit::Comp_DoNothing(u32 op) { }
|
||||
void Jit::Comp_DoNothing(MIPSOpcode op) { }
|
||||
|
||||
#define _RS ((op>>21) & 0x1F)
|
||||
#define _RT ((op>>16) & 0x1F)
|
||||
|
||||
@ -152,7 +152,7 @@ public:
|
||||
// Compiled ops should ignore delay slots
|
||||
// the compiler will take care of them by itself
|
||||
// OR NOT
|
||||
void Comp_Generic(u32 op);
|
||||
void Comp_Generic(MIPSOpcode op);
|
||||
|
||||
void RunLoopUntil(u64 globalticks);
|
||||
|
||||
@ -161,71 +161,71 @@ public:
|
||||
|
||||
void CompileDelaySlot(int flags);
|
||||
void CompileAt(u32 addr);
|
||||
void EatInstruction(u32 op);
|
||||
void Comp_RunBlock(u32 op);
|
||||
void EatInstruction(MIPSOpcode op);
|
||||
void Comp_RunBlock(MIPSOpcode op);
|
||||
|
||||
// Ops
|
||||
void Comp_ITypeMem(u32 op);
|
||||
void Comp_ITypeMem(MIPSOpcode op);
|
||||
|
||||
void Comp_RelBranch(u32 op);
|
||||
void Comp_RelBranchRI(u32 op);
|
||||
void Comp_FPUBranch(u32 op);
|
||||
void Comp_FPULS(u32 op);
|
||||
void Comp_FPUComp(u32 op);
|
||||
void Comp_Jump(u32 op);
|
||||
void Comp_JumpReg(u32 op);
|
||||
void Comp_Syscall(u32 op);
|
||||
void Comp_Break(u32 op);
|
||||
void Comp_RelBranch(MIPSOpcode op);
|
||||
void Comp_RelBranchRI(MIPSOpcode op);
|
||||
void Comp_FPUBranch(MIPSOpcode op);
|
||||
void Comp_FPULS(MIPSOpcode op);
|
||||
void Comp_FPUComp(MIPSOpcode op);
|
||||
void Comp_Jump(MIPSOpcode op);
|
||||
void Comp_JumpReg(MIPSOpcode op);
|
||||
void Comp_Syscall(MIPSOpcode op);
|
||||
void Comp_Break(MIPSOpcode op);
|
||||
|
||||
void Comp_IType(u32 op);
|
||||
void Comp_RType2(u32 op);
|
||||
void Comp_RType3(u32 op);
|
||||
void Comp_ShiftType(u32 op);
|
||||
void Comp_Allegrex(u32 op);
|
||||
void Comp_Allegrex2(u32 op);
|
||||
void Comp_VBranch(u32 op);
|
||||
void Comp_MulDivType(u32 op);
|
||||
void Comp_Special3(u32 op);
|
||||
void Comp_IType(MIPSOpcode op);
|
||||
void Comp_RType2(MIPSOpcode op);
|
||||
void Comp_RType3(MIPSOpcode op);
|
||||
void Comp_ShiftType(MIPSOpcode op);
|
||||
void Comp_Allegrex(MIPSOpcode op);
|
||||
void Comp_Allegrex2(MIPSOpcode op);
|
||||
void Comp_VBranch(MIPSOpcode op);
|
||||
void Comp_MulDivType(MIPSOpcode op);
|
||||
void Comp_Special3(MIPSOpcode op);
|
||||
|
||||
void Comp_FPU3op(u32 op);
|
||||
void Comp_FPU2op(u32 op);
|
||||
void Comp_mxc1(u32 op);
|
||||
void Comp_FPU3op(MIPSOpcode op);
|
||||
void Comp_FPU2op(MIPSOpcode op);
|
||||
void Comp_mxc1(MIPSOpcode op);
|
||||
|
||||
void Comp_DoNothing(u32 op);
|
||||
void Comp_DoNothing(MIPSOpcode op);
|
||||
|
||||
void Comp_SV(u32 op);
|
||||
void Comp_SVQ(u32 op);
|
||||
void Comp_VPFX(u32 op);
|
||||
void Comp_VVectorInit(u32 op);
|
||||
void Comp_VMatrixInit(u32 op);
|
||||
void Comp_VDot(u32 op);
|
||||
void Comp_VecDo3(u32 op);
|
||||
void Comp_VV2Op(u32 op);
|
||||
void Comp_Mftv(u32 op);
|
||||
void Comp_Vmtvc(u32 op);
|
||||
void Comp_Vmmov(u32 op);
|
||||
void Comp_VScl(u32 op);
|
||||
void Comp_Vmmul(u32 op);
|
||||
void Comp_Vmscl(u32 op);
|
||||
void Comp_Vtfm(u32 op);
|
||||
void Comp_VHdp(u32 op);
|
||||
void Comp_VCrs(u32 op);
|
||||
void Comp_VDet(u32 op);
|
||||
void Comp_Vi2x(u32 op);
|
||||
void Comp_Vx2i(u32 op);
|
||||
void Comp_Vf2i(u32 op);
|
||||
void Comp_Vi2f(u32 op);
|
||||
void Comp_Vcst(u32 op);
|
||||
void Comp_Vhoriz(u32 op);
|
||||
void Comp_VRot(u32 op);
|
||||
void Comp_VIdt(u32 op);
|
||||
void Comp_Vcmp(u32 op);
|
||||
void Comp_Vcmov(u32 op);
|
||||
void Comp_Viim(u32 op);
|
||||
void Comp_Vfim(u32 op);
|
||||
void Comp_VCrossQuat(u32 op);
|
||||
void Comp_Vsge(u32 op);
|
||||
void Comp_Vslt(u32 op);
|
||||
void Comp_SV(MIPSOpcode op);
|
||||
void Comp_SVQ(MIPSOpcode op);
|
||||
void Comp_VPFX(MIPSOpcode op);
|
||||
void Comp_VVectorInit(MIPSOpcode op);
|
||||
void Comp_VMatrixInit(MIPSOpcode op);
|
||||
void Comp_VDot(MIPSOpcode op);
|
||||
void Comp_VecDo3(MIPSOpcode op);
|
||||
void Comp_VV2Op(MIPSOpcode op);
|
||||
void Comp_Mftv(MIPSOpcode op);
|
||||
void Comp_Vmtvc(MIPSOpcode op);
|
||||
void Comp_Vmmov(MIPSOpcode op);
|
||||
void Comp_VScl(MIPSOpcode op);
|
||||
void Comp_Vmmul(MIPSOpcode op);
|
||||
void Comp_Vmscl(MIPSOpcode op);
|
||||
void Comp_Vtfm(MIPSOpcode op);
|
||||
void Comp_VHdp(MIPSOpcode op);
|
||||
void Comp_VCrs(MIPSOpcode op);
|
||||
void Comp_VDet(MIPSOpcode op);
|
||||
void Comp_Vi2x(MIPSOpcode op);
|
||||
void Comp_Vx2i(MIPSOpcode op);
|
||||
void Comp_Vf2i(MIPSOpcode op);
|
||||
void Comp_Vi2f(MIPSOpcode op);
|
||||
void Comp_Vcst(MIPSOpcode op);
|
||||
void Comp_Vhoriz(MIPSOpcode op);
|
||||
void Comp_VRot(MIPSOpcode op);
|
||||
void Comp_VIdt(MIPSOpcode op);
|
||||
void Comp_Vcmp(MIPSOpcode op);
|
||||
void Comp_Vcmov(MIPSOpcode op);
|
||||
void Comp_Viim(MIPSOpcode op);
|
||||
void Comp_Vfim(MIPSOpcode op);
|
||||
void Comp_VCrossQuat(MIPSOpcode op);
|
||||
void Comp_Vsge(MIPSOpcode op);
|
||||
void Comp_Vslt(MIPSOpcode op);
|
||||
|
||||
JitBlockCache *GetBlockCache() { return &blocks; }
|
||||
|
||||
@ -251,17 +251,17 @@ private:
|
||||
void WriteSyscallExit();
|
||||
|
||||
// Utility compilation functions
|
||||
void BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely);
|
||||
void BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely);
|
||||
void BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely);
|
||||
void BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely);
|
||||
void BranchFPFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely);
|
||||
void BranchVFPUFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely);
|
||||
void BranchRSZeroComp(MIPSOpcode op, ArmGen::CCFlags cc, bool andLink, bool likely);
|
||||
void BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely);
|
||||
|
||||
// Utilities to reduce duplicated code
|
||||
void CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b));
|
||||
void CompType3(int rd, int rs, int rt, void (ARMXEmitter::*arithOp2)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool isSub = false);
|
||||
|
||||
void CompShiftImm(u32 op, ArmGen::ShiftType shiftType);
|
||||
void CompShiftVar(u32 op, ArmGen::ShiftType shiftType);
|
||||
void CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType);
|
||||
void CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType);
|
||||
|
||||
void ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz);
|
||||
void ApplyPrefixD(const u8 *vregs, VectorSize sz);
|
||||
@ -307,7 +307,7 @@ public:
|
||||
const u8 *breakpointBailout;
|
||||
};
|
||||
|
||||
typedef void (Jit::*MIPSCompileFunc)(u32 opcode);
|
||||
typedef void (Jit::*MIPSCompileFunc)(MIPSOpcode opcode);
|
||||
|
||||
} // namespace MIPSComp
|
||||
|
||||
|
||||
@ -157,7 +157,7 @@ void JitBlockCache::FinalizeBlock(int block_num, bool block_link)
|
||||
JitBlock &b = blocks[block_num];
|
||||
|
||||
b.originalFirstOpcode = Memory::Read_Opcode_JIT(b.originalAddress);
|
||||
u32 opcode = GetEmuHackOpForBlock(block_num);
|
||||
MIPSOpcode opcode = GetEmuHackOpForBlock(block_num);
|
||||
Memory::Write_Opcode_JIT(b.originalAddress, opcode);
|
||||
|
||||
// Convert the logical address to a physical address for the block map
|
||||
@ -215,7 +215,7 @@ int binary_search(JitBlock blocks[], const u8 *baseoff, int imin, int imax)
|
||||
return -1;
|
||||
}
|
||||
|
||||
int JitBlockCache::GetBlockNumberFromEmuHackOp(u32 inst) const {
|
||||
int JitBlockCache::GetBlockNumberFromEmuHackOp(MIPSOpcode inst) const {
|
||||
if (!num_blocks || !MIPS_IS_EMUHACK(inst)) // definitely not a JIT block
|
||||
return -1;
|
||||
int off = (inst & MIPS_EMUHACK_VALUE_MASK);
|
||||
@ -224,16 +224,16 @@ int JitBlockCache::GetBlockNumberFromEmuHackOp(u32 inst) const {
|
||||
return binary_search(blocks, baseoff, 0, num_blocks-1);
|
||||
}
|
||||
|
||||
u32 JitBlockCache::GetEmuHackOpForBlock(int blockNum) const {
|
||||
MIPSOpcode JitBlockCache::GetEmuHackOpForBlock(int blockNum) const {
|
||||
int off = (int)(blocks[blockNum].normalEntry - codeBlock_->GetBasePtr());
|
||||
return (MIPS_EMUHACK_OPCODE | off);
|
||||
return MIPSOpcode(MIPS_EMUHACK_OPCODE | off);
|
||||
}
|
||||
|
||||
int JitBlockCache::GetBlockNumberFromStartAddress(u32 addr)
|
||||
{
|
||||
if (!blocks)
|
||||
return -1;
|
||||
u32 inst = Memory::Read_U32(addr);
|
||||
MIPSOpcode inst = MIPSOpcode(Memory::Read_U32(addr));
|
||||
int bl = GetBlockNumberFromEmuHackOp(inst);
|
||||
if (bl < 0)
|
||||
return -1;
|
||||
@ -249,12 +249,12 @@ void JitBlockCache::GetBlockNumbersFromAddress(u32 em_address, std::vector<int>
|
||||
block_numbers->push_back(i);
|
||||
}
|
||||
|
||||
u32 JitBlockCache::GetOriginalFirstOp(int block_num)
|
||||
MIPSOpcode JitBlockCache::GetOriginalFirstOp(int block_num)
|
||||
{
|
||||
if (block_num >= num_blocks || block_num < 0)
|
||||
{
|
||||
//PanicAlert("JitBlockCache::GetOriginalFirstOp - block_num = %u is out of range", block_num);
|
||||
return block_num;
|
||||
return MIPSOpcode(block_num);
|
||||
}
|
||||
return blocks[block_num].originalFirstOpcode;
|
||||
}
|
||||
@ -337,8 +337,8 @@ void JitBlockCache::DestroyBlock(int block_num, bool invalidate)
|
||||
return;
|
||||
}
|
||||
b.invalid = true;
|
||||
if (Memory::ReadUnchecked_U32(b.originalAddress) == GetEmuHackOpForBlock(block_num))
|
||||
Memory::WriteUnchecked_U32(b.originalFirstOpcode, b.originalAddress);
|
||||
if (Memory::ReadUnchecked_U32(b.originalAddress) == GetEmuHackOpForBlock(block_num).encoding)
|
||||
Memory::Write_Opcode_JIT(b.originalAddress, b.originalFirstOpcode);
|
||||
b.normalEntry = 0;
|
||||
|
||||
UnlinkBlock(block_num);
|
||||
|
||||
@ -65,7 +65,7 @@ struct JitBlock {
|
||||
u32 exitAddress[MAX_JIT_BLOCK_EXITS]; // 0xFFFFFFFF == unknown
|
||||
|
||||
u32 originalAddress;
|
||||
u32 originalFirstOpcode; //to be able to restore
|
||||
MIPSOpcode originalFirstOpcode; //to be able to restore
|
||||
u16 codeSize;
|
||||
u16 originalSize;
|
||||
u16 blockNum;
|
||||
@ -107,9 +107,9 @@ public:
|
||||
// Returns a list of block numbers - only one block can start at a particular address, but they CAN overlap.
|
||||
// This one is slow so should only be used for one-shots from the debugger UI, not for anything during runtime.
|
||||
void GetBlockNumbersFromAddress(u32 em_address, std::vector<int> *block_numbers);
|
||||
int GetBlockNumberFromEmuHackOp(u32 inst) const;
|
||||
int GetBlockNumberFromEmuHackOp(MIPSOpcode inst) const;
|
||||
|
||||
u32 GetOriginalFirstOp(int block_num);
|
||||
MIPSOpcode GetOriginalFirstOp(int block_num);
|
||||
|
||||
// DOES NOT WORK CORRECTLY WITH JIT INLINING
|
||||
void InvalidateICache(u32 address, const u32 length);
|
||||
@ -120,7 +120,7 @@ private:
|
||||
void LinkBlock(int i);
|
||||
void UnlinkBlock(int i);
|
||||
|
||||
u32 GetEmuHackOpForBlock(int block_num) const;
|
||||
MIPSOpcode GetEmuHackOpForBlock(int block_num) const;
|
||||
|
||||
MIPSState *mips;
|
||||
CodeBlock *codeBlock_;
|
||||
|
||||
@ -17,10 +17,13 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "../../Globals.h"
|
||||
#include "../CPU.h"
|
||||
#include "Globals.h"
|
||||
#include "Core/MemMap.h"
|
||||
#include "Core/CPU.h"
|
||||
#include "util/random/rng.h"
|
||||
|
||||
typedef Memory::Opcode MIPSOpcode;
|
||||
|
||||
enum
|
||||
{
|
||||
MIPS_REG_ZERO=0,
|
||||
|
||||
@ -16,186 +16,134 @@
|
||||
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
|
||||
|
||||
#include <map>
|
||||
#include "../../Globals.h"
|
||||
#include "Globals.h"
|
||||
|
||||
#include "MIPS.h"
|
||||
#include "MIPSTables.h"
|
||||
#include "MIPSAnalyst.h"
|
||||
#include "MIPSCodeUtils.h"
|
||||
#include "../Debugger/SymbolMap.h"
|
||||
#include "../Debugger/DebugInterface.h"
|
||||
#include "Core/MIPS/MIPS.h"
|
||||
#include "Core/MIPS/MIPSTables.h"
|
||||
#include "Core/MIPS/MIPSAnalyst.h"
|
||||
#include "Core/MIPS/MIPSCodeUtils.h"
|
||||
#include "Core/Debugger/SymbolMap.h"
|
||||
#include "Core/Debugger/DebugInterface.h"
|
||||
|
||||
using namespace MIPSCodeUtils;
|
||||
using namespace std;
|
||||
|
||||
namespace MIPSAnalyst
|
||||
{
|
||||
RegisterAnalysisResults regAnal[32];
|
||||
RegisterAnalysisResults total[32];
|
||||
int numAnalysisDone=0;
|
||||
|
||||
int GetOutReg(u32 op)
|
||||
{
|
||||
u32 opinfo = MIPSGetInfo(op);
|
||||
if (opinfo & OUT_RT)
|
||||
return MIPS_GET_RT(op);
|
||||
if (opinfo & OUT_RD)
|
||||
return MIPS_GET_RD(op);
|
||||
if (opinfo & OUT_RA)
|
||||
return MIPS_REG_RA;
|
||||
// Only can ever output a single reg.
|
||||
int GetOutGPReg(MIPSOpcode op) {
|
||||
MIPSInfo opinfo = MIPSGetInfo(op);
|
||||
if ((opinfo & IS_VFPU) == 0) {
|
||||
if (opinfo & OUT_RT) {
|
||||
return MIPS_GET_RT(op);
|
||||
}
|
||||
if (opinfo & OUT_RD) {
|
||||
return MIPS_GET_RD(op);
|
||||
}
|
||||
if (opinfo & OUT_RA) {
|
||||
return MIPS_REG_RA;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool ReadsFromReg(u32 op, u32 reg)
|
||||
{
|
||||
u32 opinfo = MIPSGetInfo(op);
|
||||
if (opinfo & IN_RT)
|
||||
{
|
||||
if (MIPS_GET_RT(opinfo) == reg)
|
||||
bool ReadsFromGPReg(MIPSOpcode op, u32 reg) {
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if ((info & IS_VFPU) == 0) {
|
||||
if ((info & IN_RS) != 0 && MIPS_GET_RS(op) == reg) {
|
||||
return true;
|
||||
}
|
||||
if (opinfo & IN_RS)
|
||||
{
|
||||
if (MIPS_GET_RS(opinfo) == reg)
|
||||
return true;
|
||||
}
|
||||
return false; //TODO: there are more cases!
|
||||
}
|
||||
|
||||
// TODO: Remove me?
|
||||
bool IsDelaySlotNice(u32 branch, u32 delayslot)
|
||||
{
|
||||
int outReg = GetOutReg(delayslot);
|
||||
if (outReg != -1)
|
||||
{
|
||||
if (ReadsFromReg(branch, outReg))
|
||||
{
|
||||
return false; //evil :(
|
||||
}
|
||||
else
|
||||
{
|
||||
return false; //aggh this should be true but doesn't work
|
||||
if ((info & IN_RT) != 0 && MIPS_GET_RT(op) == reg) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// Check for FPU flag
|
||||
if ((MIPSGetInfo(delayslot) & OUT_FPUFLAG) && (MIPSGetInfo(branch) & IN_FPUFLAG))
|
||||
return false;
|
||||
|
||||
return true; //nice :)
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2)
|
||||
{
|
||||
bool IsDelaySlotNiceReg(MIPSOpcode branchOp, MIPSOpcode op, int reg1, int reg2) {
|
||||
// $0 is never an out reg, it's always 0.
|
||||
if (reg1 != 0 && GetOutReg(op) == reg1)
|
||||
if (reg1 != 0 && GetOutGPReg(op) == reg1) {
|
||||
return false;
|
||||
if (reg2 != 0 && GetOutReg(op) == reg2)
|
||||
}
|
||||
if (reg2 != 0 && GetOutGPReg(op) == reg2) {
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool IsDelaySlotNiceVFPU(u32 branchOp, u32 op)
|
||||
{
|
||||
bool IsDelaySlotNiceVFPU(MIPSOpcode branchOp, MIPSOpcode op) {
|
||||
// TODO: There may be IS_VFPU cases which are safe...
|
||||
return (MIPSGetInfo(op) & IS_VFPU) == 0;
|
||||
}
|
||||
|
||||
bool IsDelaySlotNiceFPU(u32 branchOp, u32 op)
|
||||
{
|
||||
bool IsDelaySlotNiceFPU(MIPSOpcode branchOp, MIPSOpcode op) {
|
||||
return (MIPSGetInfo(op) & OUT_FPUFLAG) == 0;
|
||||
}
|
||||
|
||||
bool IsSyscall(u32 op)
|
||||
{
|
||||
bool IsSyscall(MIPSOpcode op) {
|
||||
// Syscalls look like this: 0000 00-- ---- ---- ---- --00 1100
|
||||
return (op >> 26) == 0 && (op & 0x3f) == 12;
|
||||
}
|
||||
|
||||
void Analyze(u32 address)
|
||||
{
|
||||
AnalysisResults Analyze(u32 address) {
|
||||
const int MAX_ANALYZE = 10000;
|
||||
|
||||
AnalysisResults results;
|
||||
|
||||
//set everything to -1 (FF)
|
||||
memset(regAnal, 255, sizeof(AnalysisResults)*32);
|
||||
for (int i=0; i<32; i++)
|
||||
{
|
||||
regAnal[i].used=false;
|
||||
regAnal[i].readCount=0;
|
||||
regAnal[i].writeCount=0;
|
||||
regAnal[i].readAsAddrCount=0;
|
||||
memset(&results, 255, sizeof(AnalysisResults));
|
||||
for (int i = 0; i < MIPS_NUM_GPRS; i++) {
|
||||
results.r[i].used = false;
|
||||
results.r[i].readCount = 0;
|
||||
results.r[i].writeCount = 0;
|
||||
results.r[i].readAsAddrCount = 0;
|
||||
}
|
||||
|
||||
u32 addr = address;
|
||||
bool exitFlag = false;
|
||||
while (true)
|
||||
{
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
u32 info = MIPSGetInfo(op);
|
||||
for (u32 addr = address, endAddr = address + MAX_ANALYZE; addr <= endAddr; addr += 4) {
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
|
||||
for (int reg=0; reg < 32; reg++)
|
||||
{
|
||||
int rs = MIPS_GET_RS(op);
|
||||
int rt = MIPS_GET_RT(op);
|
||||
int rd = MIPS_GET_RD(op);
|
||||
int rs = MIPS_GET_RS(op);
|
||||
int rt = MIPS_GET_RT(op);
|
||||
|
||||
if (
|
||||
((info & IN_RS) && (info & IN_RS_ADDR) == IN_RS && (rs == reg)) ||
|
||||
((info & IN_RT) && (rt == reg)))
|
||||
{
|
||||
if (regAnal[reg].firstRead == -1)
|
||||
regAnal[reg].firstRead = addr;
|
||||
regAnal[reg].lastRead = addr;
|
||||
regAnal[reg].readCount++;
|
||||
regAnal[reg].used=true;
|
||||
}
|
||||
if (
|
||||
((info & IN_RS_ADDR) && (rs == reg))
|
||||
)
|
||||
{
|
||||
if (regAnal[reg].firstReadAsAddr == -1)
|
||||
regAnal[reg].firstReadAsAddr = addr;
|
||||
regAnal[reg].lastReadAsAddr = addr;
|
||||
regAnal[reg].readAsAddrCount++;
|
||||
regAnal[reg].used=true;
|
||||
}
|
||||
if (
|
||||
((info & OUT_RT) && (rt == reg)) ||
|
||||
((info & OUT_RD) && (rd == reg)) ||
|
||||
((info & OUT_RA) && (reg == MIPS_REG_RA))
|
||||
)
|
||||
{
|
||||
if (regAnal[reg].firstWrite == -1)
|
||||
regAnal[reg].firstWrite = addr;
|
||||
regAnal[reg].lastWrite = addr;
|
||||
regAnal[reg].writeCount++;
|
||||
regAnal[reg].used=true;
|
||||
if (info & IN_RS) {
|
||||
if ((info & IN_RS_ADDR) == IN_RS_ADDR) {
|
||||
results.r[rs].MarkReadAsAddr(addr);
|
||||
} else {
|
||||
results.r[rs].MarkRead(addr);
|
||||
}
|
||||
}
|
||||
|
||||
if (exitFlag) //delay slot done, let's quit!
|
||||
break;
|
||||
|
||||
if ((info & IS_JUMP) || (info & IS_CONDBRANCH))
|
||||
{
|
||||
exitFlag = true; // now do the delay slot
|
||||
if (info & IN_RT) {
|
||||
results.r[rt].MarkRead(addr);
|
||||
}
|
||||
|
||||
addr += 4;
|
||||
int outReg = GetOutGPReg(op);
|
||||
if (outReg != -1) {
|
||||
results.r[outReg].MarkWrite(addr);
|
||||
}
|
||||
|
||||
if (info & DELAYSLOT)
|
||||
{
|
||||
// Let's just finish the delay slot before bailing.
|
||||
endAddr = addr + 4;
|
||||
}
|
||||
}
|
||||
|
||||
int numUsedRegs=0;
|
||||
static int totalUsedRegs=0;
|
||||
static int numAnalyzings=0;
|
||||
for (int i=0; i<32; i++)
|
||||
{
|
||||
if (regAnal[i].used)
|
||||
for (int i = 0; i < MIPS_NUM_GPRS; i++) {
|
||||
if (results.r[i].used) {
|
||||
numUsedRegs++;
|
||||
}
|
||||
}
|
||||
totalUsedRegs+=numUsedRegs;
|
||||
numAnalyzings++;
|
||||
DEBUG_LOG(CPU,"[ %08x ] Used regs: %i Average: %f",address,numUsedRegs,(float)totalUsedRegs/(float)numAnalyzings);
|
||||
|
||||
return results;
|
||||
}
|
||||
|
||||
|
||||
@ -240,8 +188,8 @@ namespace MIPSAnalyst
|
||||
{
|
||||
while (true)
|
||||
{
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
|
||||
if ((info & IN_RS) && (MIPS_GET_RS(op) == reg))
|
||||
return true;
|
||||
@ -271,8 +219,8 @@ namespace MIPSAnalyst
|
||||
for (u32 addr = f.start; addr <= f.end; addr += 4)
|
||||
{
|
||||
u32 validbits = 0xFFFFFFFF;
|
||||
u32 instr = Memory::Read_Instruction(addr);
|
||||
u32 flags = MIPSGetInfo(instr);
|
||||
MIPSOpcode instr = Memory::Read_Instruction(addr);
|
||||
MIPSInfo flags = MIPSGetInfo(instr);
|
||||
if (flags & IN_IMM16)
|
||||
validbits&=~0xFFFF;
|
||||
if (flags & IN_IMM26)
|
||||
@ -303,7 +251,7 @@ namespace MIPSAnalyst
|
||||
continue;
|
||||
}
|
||||
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
u32 target = GetBranchTargetNoRA(addr);
|
||||
if (target != INVALIDTARGET)
|
||||
{
|
||||
@ -452,10 +400,10 @@ namespace MIPSAnalyst
|
||||
LOG(CPU,"Precompiled %i straight leaf functions",count);*/
|
||||
}
|
||||
|
||||
std::vector<int> GetInputRegs(u32 op)
|
||||
std::vector<int> GetInputRegs(MIPSOpcode op)
|
||||
{
|
||||
std::vector<int> vec;
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if ((info & IS_VFPU) == 0)
|
||||
{
|
||||
if (info & IN_RS) vec.push_back(MIPS_GET_RS(op));
|
||||
@ -463,10 +411,10 @@ namespace MIPSAnalyst
|
||||
}
|
||||
return vec;
|
||||
}
|
||||
std::vector<int> GetOutputRegs(u32 op)
|
||||
std::vector<int> GetOutputRegs(MIPSOpcode op)
|
||||
{
|
||||
std::vector<int> vec;
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if ((info & IS_VFPU) == 0)
|
||||
{
|
||||
if (info & OUT_RD) vec.push_back(MIPS_GET_RD(op));
|
||||
@ -489,8 +437,8 @@ namespace MIPSAnalyst
|
||||
info.opcodeAddress = address;
|
||||
info.encodedOpcode = Memory::Read_Instruction(address);
|
||||
|
||||
u32 op = info.encodedOpcode;
|
||||
u32 opInfo = MIPSGetInfo(op);
|
||||
MIPSOpcode op = info.encodedOpcode;
|
||||
MIPSInfo opInfo = MIPSGetInfo(op);
|
||||
info.isLikelyBranch = (opInfo & LIKELY) != 0;
|
||||
|
||||
//j , jal, ...
|
||||
|
||||
@ -17,15 +17,16 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "../../Globals.h"
|
||||
#include "Globals.h"
|
||||
#include "Core/MIPS/MIPS.h"
|
||||
|
||||
class DebugInterface;
|
||||
|
||||
namespace MIPSAnalyst
|
||||
{
|
||||
void Analyze(u32 address);
|
||||
struct RegisterAnalysisResults
|
||||
{
|
||||
const int MIPS_NUM_GPRS = 32;
|
||||
|
||||
struct RegisterAnalysisResults {
|
||||
bool used;
|
||||
int firstRead;
|
||||
int lastRead;
|
||||
@ -37,32 +38,56 @@ namespace MIPSAnalyst
|
||||
int readCount;
|
||||
int writeCount;
|
||||
int readAsAddrCount;
|
||||
bool usesVFPU;
|
||||
|
||||
int TotalReadCount() {return readCount + readAsAddrCount;}
|
||||
int FirstRead() {return firstReadAsAddr < firstRead ? firstReadAsAddr : firstRead;}
|
||||
int LastRead() {return lastReadAsAddr > lastRead ? lastReadAsAddr : lastRead;}
|
||||
int TotalReadCount() const { return readCount + readAsAddrCount; }
|
||||
int FirstRead() const { return firstReadAsAddr < firstRead ? firstReadAsAddr : firstRead; }
|
||||
int LastRead() const { return lastReadAsAddr > lastRead ? lastReadAsAddr : lastRead; }
|
||||
|
||||
void MarkRead(u32 addr) {
|
||||
if (firstRead == -1)
|
||||
firstRead = addr;
|
||||
lastRead = addr;
|
||||
readCount++;
|
||||
used = true;
|
||||
}
|
||||
|
||||
void MarkReadAsAddr(u32 addr) {
|
||||
if (firstReadAsAddr == -1)
|
||||
firstReadAsAddr = addr;
|
||||
lastReadAsAddr = addr;
|
||||
readAsAddrCount++;
|
||||
used = true;
|
||||
}
|
||||
|
||||
void MarkWrite(u32 addr) {
|
||||
if (firstWrite == -1)
|
||||
firstWrite = addr;
|
||||
lastWrite = addr;
|
||||
writeCount++;
|
||||
used = true;
|
||||
}
|
||||
};
|
||||
|
||||
struct AnalysisResults
|
||||
{
|
||||
int x;
|
||||
struct AnalysisResults {
|
||||
RegisterAnalysisResults r[MIPS_NUM_GPRS];
|
||||
};
|
||||
|
||||
AnalysisResults Analyze(u32 address);
|
||||
|
||||
|
||||
bool IsRegisterUsed(u32 reg, u32 addr);
|
||||
void ScanForFunctions(u32 startAddr, u32 endAddr);
|
||||
void CompileLeafs();
|
||||
|
||||
std::vector<int> GetInputRegs(u32 op);
|
||||
std::vector<int> GetOutputRegs(u32 op);
|
||||
std::vector<int> GetInputRegs(MIPSOpcode op);
|
||||
std::vector<int> GetOutputRegs(MIPSOpcode op);
|
||||
|
||||
int GetOutReg(u32 op);
|
||||
bool ReadsFromReg(u32 op, u32 reg);
|
||||
bool IsDelaySlotNice(u32 branch, u32 delayslot);
|
||||
bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2 = 0);
|
||||
bool IsDelaySlotNiceVFPU(u32 branchOp, u32 op);
|
||||
bool IsDelaySlotNiceFPU(u32 branchOp, u32 op);
|
||||
bool IsSyscall(u32 op);
|
||||
int GetOutGPReg(MIPSOpcode op);
|
||||
bool ReadsFromGPReg(MIPSOpcode op, u32 reg);
|
||||
bool IsDelaySlotNiceReg(MIPSOpcode branchOp, MIPSOpcode op, int reg1, int reg2 = 0);
|
||||
bool IsDelaySlotNiceVFPU(MIPSOpcode branchOp, MIPSOpcode op);
|
||||
bool IsDelaySlotNiceFPU(MIPSOpcode branchOp, MIPSOpcode op);
|
||||
bool IsSyscall(MIPSOpcode op);
|
||||
|
||||
void Shutdown();
|
||||
|
||||
@ -70,7 +95,7 @@ namespace MIPSAnalyst
|
||||
{
|
||||
DebugInterface* cpu;
|
||||
u32 opcodeAddress;
|
||||
u32 encodedOpcode;
|
||||
MIPSOpcode encodedOpcode;
|
||||
|
||||
// shared between branches and conditional moves
|
||||
bool isConditional;
|
||||
|
||||
@ -31,10 +31,10 @@ namespace MIPSCodeUtils
|
||||
|
||||
u32 GetJumpTarget(u32 addr)
|
||||
{
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
if (op)
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
if (op != 0)
|
||||
{
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if ((info & IS_JUMP) && (info & IN_IMM26))
|
||||
{
|
||||
u32 target = (addr & 0xF0000000) | ((op&0x03FFFFFF) << 2);
|
||||
@ -49,10 +49,10 @@ namespace MIPSCodeUtils
|
||||
|
||||
u32 GetBranchTarget(u32 addr)
|
||||
{
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
if (op)
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
if (op != 0)
|
||||
{
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if (info & IS_CONDBRANCH)
|
||||
{
|
||||
return addr + 4 + ((signed short)(op&0xFFFF)<<2);
|
||||
@ -66,10 +66,10 @@ namespace MIPSCodeUtils
|
||||
|
||||
u32 GetBranchTargetNoRA(u32 addr)
|
||||
{
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
if (op)
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
if (op != 0)
|
||||
{
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if ((info & IS_CONDBRANCH) && !(info & OUT_RA))
|
||||
{
|
||||
return addr + 4 + ((signed short)(op&0xFFFF)<<2);
|
||||
@ -83,10 +83,10 @@ namespace MIPSCodeUtils
|
||||
|
||||
u32 GetSureBranchTarget(u32 addr)
|
||||
{
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
if (op)
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
if (op != 0)
|
||||
{
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if (info & IS_CONDBRANCH)
|
||||
{
|
||||
bool sure;
|
||||
@ -133,7 +133,7 @@ namespace MIPSCodeUtils
|
||||
return INVALIDTARGET;
|
||||
}
|
||||
|
||||
bool IsVFPUBranch(u32 op) {
|
||||
bool IsVFPUBranch(MIPSOpcode op) {
|
||||
return (MIPSGetInfo(op) & (IS_VFPU | IS_CONDBRANCH)) == (IS_VFPU | IS_CONDBRANCH);
|
||||
}
|
||||
}
|
||||
|
||||
@ -57,5 +57,5 @@ namespace MIPSCodeUtils
|
||||
u32 GetBranchTargetNoRA(u32 addr);
|
||||
u32 GetJumpTarget(u32 addr);
|
||||
u32 GetSureBranchTarget(u32 addr);
|
||||
bool IsVFPUBranch(u32 op);
|
||||
bool IsVFPUBranch(MIPSOpcode op);
|
||||
}
|
||||
|
||||
@ -56,12 +56,12 @@ namespace MIPSDis
|
||||
return temp;
|
||||
}
|
||||
|
||||
void Dis_Generic(u32 op, char *out)
|
||||
void Dis_Generic(MIPSOpcode op, char *out)
|
||||
{
|
||||
sprintf(out, "%s\t --- unknown ---", MIPSGetName(op));
|
||||
}
|
||||
|
||||
void Dis_mxc1(u32 op, char *out)
|
||||
void Dis_mxc1(MIPSOpcode op, char *out)
|
||||
{
|
||||
int fs = _FS;
|
||||
int rt = _RT;
|
||||
@ -69,7 +69,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s",name,RN(rt),FN(fs));
|
||||
}
|
||||
|
||||
void Dis_FPU3op(u32 op, char *out)
|
||||
void Dis_FPU3op(MIPSOpcode op, char *out)
|
||||
{
|
||||
int ft = _FT;
|
||||
int fs = _FS;
|
||||
@ -78,7 +78,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s, %s",name,FN(fd),FN(fs),FN(ft));
|
||||
}
|
||||
|
||||
void Dis_FPU2op(u32 op, char *out)
|
||||
void Dis_FPU2op(MIPSOpcode op, char *out)
|
||||
{
|
||||
int fs = _FS;
|
||||
int fd = _FD;;
|
||||
@ -86,7 +86,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s",name,FN(fd),FN(fs));
|
||||
}
|
||||
|
||||
void Dis_FPULS(u32 op, char *out)
|
||||
void Dis_FPULS(MIPSOpcode op, char *out)
|
||||
{
|
||||
int offset = (signed short)(op&0xFFFF);
|
||||
int ft = _FT;
|
||||
@ -94,7 +94,7 @@ namespace MIPSDis
|
||||
const char *name = MIPSGetName(op);
|
||||
sprintf(out, "%s\t%s, %s(%s)",name,FN(ft),SignedHex(offset),RN(rs));
|
||||
}
|
||||
void Dis_FPUComp(u32 op, char *out)
|
||||
void Dis_FPUComp(MIPSOpcode op, char *out)
|
||||
{
|
||||
int fs = _FS;
|
||||
int ft = _FT;
|
||||
@ -102,7 +102,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s",name,FN(fs),FN(ft));
|
||||
}
|
||||
|
||||
void Dis_FPUBranch(u32 op, char *out)
|
||||
void Dis_FPUBranch(MIPSOpcode op, char *out)
|
||||
{
|
||||
u32 off = disPC;
|
||||
int imm = (signed short)(op&0xFFFF)<<2;
|
||||
@ -111,7 +111,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t->$%08x",name,off);
|
||||
}
|
||||
|
||||
void Dis_RelBranch(u32 op, char *out)
|
||||
void Dis_RelBranch(MIPSOpcode op, char *out)
|
||||
{
|
||||
u32 off = disPC;
|
||||
int imm = (signed short)(op&0xFFFF)<<2;
|
||||
@ -122,7 +122,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, ->$%08x",name,RN(rs),off);
|
||||
}
|
||||
|
||||
void Dis_Syscall(u32 op, char *out)
|
||||
void Dis_Syscall(MIPSOpcode op, char *out)
|
||||
{
|
||||
u32 callno = (op>>6) & 0xFFFFF; //20 bits
|
||||
int funcnum = callno & 0xFFF;
|
||||
@ -130,20 +130,20 @@ namespace MIPSDis
|
||||
sprintf(out, "syscall\t %s",/*PSPHLE::GetModuleName(modulenum),*/GetFuncName(modulenum, funcnum));
|
||||
}
|
||||
|
||||
void Dis_ToHiloTransfer(u32 op, char *out)
|
||||
void Dis_ToHiloTransfer(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rs = _RS;
|
||||
const char *name = MIPSGetName(op);
|
||||
sprintf(out, "%s\t%s",name,RN(rs));
|
||||
}
|
||||
void Dis_FromHiloTransfer(u32 op, char *out)
|
||||
void Dis_FromHiloTransfer(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rd = _RD;
|
||||
const char *name = MIPSGetName(op);
|
||||
sprintf(out, "%s\t%s",name,RN(rd));
|
||||
}
|
||||
|
||||
void Dis_RelBranch2(u32 op, char *out)
|
||||
void Dis_RelBranch2(MIPSOpcode op, char *out)
|
||||
{
|
||||
u32 off = disPC;
|
||||
int imm = (signed short)(op&0xFFFF)<<2;
|
||||
@ -161,7 +161,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s, ->$%08x",name,RN(rt),RN(rs),off);
|
||||
}
|
||||
|
||||
void Dis_IType(u32 op, char *out)
|
||||
void Dis_IType(MIPSOpcode op, char *out)
|
||||
{
|
||||
s32 simm = (s32)(s16)(op & 0xFFFF);
|
||||
u32 uimm = (u32)(u16)(op & 0xFFFF);
|
||||
@ -185,7 +185,7 @@ namespace MIPSDis
|
||||
break;
|
||||
}
|
||||
}
|
||||
void Dis_ori(u32 op, char *out)
|
||||
void Dis_ori(MIPSOpcode op, char *out)
|
||||
{
|
||||
s32 simm = (s32)(s16)(op & 0xFFFF);
|
||||
u32 uimm = (u32)(u16)(op & 0xFFFF);
|
||||
@ -198,7 +198,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s, 0x%X",name,RN(rt),RN(rs),uimm);
|
||||
}
|
||||
|
||||
void Dis_IType1(u32 op, char *out)
|
||||
void Dis_IType1(MIPSOpcode op, char *out)
|
||||
{
|
||||
u32 uimm = (u32)(u16)(op & 0xFFFF);
|
||||
int rt = _RT;
|
||||
@ -206,7 +206,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, 0x%X",name,RN(rt),uimm);
|
||||
}
|
||||
|
||||
void Dis_addi(u32 op, char *out)
|
||||
void Dis_addi(MIPSOpcode op, char *out)
|
||||
{
|
||||
int imm = (signed short)(op&0xFFFF);
|
||||
int rt = _RT;
|
||||
@ -217,7 +217,7 @@ namespace MIPSDis
|
||||
Dis_IType(op,out);
|
||||
}
|
||||
|
||||
void Dis_ITypeMem(u32 op, char *out)
|
||||
void Dis_ITypeMem(MIPSOpcode op, char *out)
|
||||
{
|
||||
int imm = (signed short)(op&0xFFFF);
|
||||
int rt = _RT;
|
||||
@ -226,7 +226,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s(%s)",name,RN(rt),SignedHex(imm),RN(rs));
|
||||
}
|
||||
|
||||
void Dis_RType2(u32 op, char *out)
|
||||
void Dis_RType2(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rs = _RS;
|
||||
int rd = _RD;
|
||||
@ -234,7 +234,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s",name,RN(rd),RN(rs));
|
||||
}
|
||||
|
||||
void Dis_RType3(u32 op, char *out)
|
||||
void Dis_RType3(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rs = _RS;
|
||||
@ -243,7 +243,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s, %s",name,RN(rd),RN(rs),RN(rt));
|
||||
}
|
||||
|
||||
void Dis_addu(u32 op, char *out)
|
||||
void Dis_addu(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rs = _RS;
|
||||
@ -259,7 +259,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s, %s",name,RN(rd),RN(rs),RN(rt));
|
||||
}
|
||||
|
||||
void Dis_ShiftType(u32 op, char *out)
|
||||
void Dis_ShiftType(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rs = _RS;
|
||||
@ -273,7 +273,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %s, 0x%X",name,RN(rd),RN(rt),sa);
|
||||
}
|
||||
|
||||
void Dis_VarShiftType(u32 op, char *out)
|
||||
void Dis_VarShiftType(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rs = _RS;
|
||||
@ -283,7 +283,7 @@ namespace MIPSDis
|
||||
}
|
||||
|
||||
|
||||
void Dis_MulDivType(u32 op, char *out)
|
||||
void Dis_MulDivType(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rs = _RS;
|
||||
@ -292,7 +292,7 @@ namespace MIPSDis
|
||||
}
|
||||
|
||||
|
||||
void Dis_Special3(u32 op, char *out)
|
||||
void Dis_Special3(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rs = _RS;
|
||||
int Rt = _RT;
|
||||
@ -316,14 +316,14 @@ namespace MIPSDis
|
||||
}
|
||||
}
|
||||
|
||||
void Dis_JumpType(u32 op, char *out)
|
||||
void Dis_JumpType(MIPSOpcode op, char *out)
|
||||
{
|
||||
u32 off = ((op & 0x03FFFFFF) << 2);
|
||||
u32 addr = (disPC & 0xF0000000) | off;
|
||||
const char *name = MIPSGetName(op);
|
||||
sprintf(out, "%s\t->$%08x",name,addr);
|
||||
}
|
||||
void Dis_JumpRegType(u32 op, char *out)
|
||||
void Dis_JumpRegType(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rs = (op>>21)&0x1f;
|
||||
const char *name = MIPSGetName(op);
|
||||
@ -331,7 +331,7 @@ namespace MIPSDis
|
||||
|
||||
}
|
||||
|
||||
void Dis_Allegrex(u32 op, char *out)
|
||||
void Dis_Allegrex(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rd = _RD;
|
||||
@ -339,7 +339,7 @@ namespace MIPSDis
|
||||
sprintf(out,"%s\t%s,%s",name,RN(rd),RN(rt));
|
||||
}
|
||||
|
||||
void Dis_Allegrex2(u32 op, char *out)
|
||||
void Dis_Allegrex2(MIPSOpcode op, char *out)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rd = _RD;
|
||||
@ -347,7 +347,7 @@ namespace MIPSDis
|
||||
sprintf(out,"%s\t%s,%s",name,RN(rd),RN(rt));
|
||||
}
|
||||
|
||||
void Dis_Emuhack(u32 op, char *out)
|
||||
void Dis_Emuhack(MIPSOpcode op, char *out)
|
||||
{
|
||||
//const char *name = MIPSGetName(op);
|
||||
//sprintf(out,"%s\t-",name);
|
||||
|
||||
@ -17,45 +17,46 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "../../Globals.h"
|
||||
#include "Globals.h"
|
||||
#include "Core/MIPS/MIPS.h"
|
||||
|
||||
extern u32 disPC;
|
||||
|
||||
namespace MIPSDis
|
||||
{
|
||||
void Dis_Unknown(u32 op, char *out);
|
||||
void Dis_Unimpl(u32 op, char *out);
|
||||
void Dis_Syscall(u32 op, char *out);
|
||||
void Dis_Unknown(MIPSOpcode op, char *out);
|
||||
void Dis_Unimpl(MIPSOpcode op, char *out);
|
||||
void Dis_Syscall(MIPSOpcode op, char *out);
|
||||
|
||||
void Dis_mxc1(u32 op, char *out);
|
||||
void Dis_addi(u32 op, char *out);
|
||||
void Dis_addu(u32 op, char *out);
|
||||
void Dis_RelBranch2(u32 op, char *out);
|
||||
void Dis_RelBranch(u32 op, char *out);
|
||||
void Dis_Generic(u32 op, char *out);
|
||||
void Dis_IType(u32 op, char *out);
|
||||
void Dis_IType1(u32 op, char *out);
|
||||
void Dis_ITypeMem(u32 op, char *out);
|
||||
void Dis_RType2(u32 op, char *out);
|
||||
void Dis_RType3(u32 op, char *out);
|
||||
void Dis_MulDivType(u32 op, char *out);
|
||||
void Dis_ShiftType(u32 op, char *out);
|
||||
void Dis_VarShiftType(u32 op, char *out);
|
||||
void Dis_FPU3op(u32 op, char *out);
|
||||
void Dis_FPU2op(u32 op, char *out);
|
||||
void Dis_FPULS(u32 op, char *out);
|
||||
void Dis_FPUComp(u32 op, char *out);
|
||||
void Dis_FPUBranch(u32 op, char *out);
|
||||
void Dis_ori(u32 op, char *out);
|
||||
void Dis_Special3(u32 op, char *out);
|
||||
void Dis_mxc1(MIPSOpcode op, char *out);
|
||||
void Dis_addi(MIPSOpcode op, char *out);
|
||||
void Dis_addu(MIPSOpcode op, char *out);
|
||||
void Dis_RelBranch2(MIPSOpcode op, char *out);
|
||||
void Dis_RelBranch(MIPSOpcode op, char *out);
|
||||
void Dis_Generic(MIPSOpcode op, char *out);
|
||||
void Dis_IType(MIPSOpcode op, char *out);
|
||||
void Dis_IType1(MIPSOpcode op, char *out);
|
||||
void Dis_ITypeMem(MIPSOpcode op, char *out);
|
||||
void Dis_RType2(MIPSOpcode op, char *out);
|
||||
void Dis_RType3(MIPSOpcode op, char *out);
|
||||
void Dis_MulDivType(MIPSOpcode op, char *out);
|
||||
void Dis_ShiftType(MIPSOpcode op, char *out);
|
||||
void Dis_VarShiftType(MIPSOpcode op, char *out);
|
||||
void Dis_FPU3op(MIPSOpcode op, char *out);
|
||||
void Dis_FPU2op(MIPSOpcode op, char *out);
|
||||
void Dis_FPULS(MIPSOpcode op, char *out);
|
||||
void Dis_FPUComp(MIPSOpcode op, char *out);
|
||||
void Dis_FPUBranch(MIPSOpcode op, char *out);
|
||||
void Dis_ori(MIPSOpcode op, char *out);
|
||||
void Dis_Special3(MIPSOpcode op, char *out);
|
||||
|
||||
void Dis_ToHiloTransfer(u32 op, char *out);
|
||||
void Dis_FromHiloTransfer(u32 op, char *out);
|
||||
void Dis_JumpType(u32 op, char *out);
|
||||
void Dis_JumpRegType(u32 op, char *out);
|
||||
void Dis_ToHiloTransfer(MIPSOpcode op, char *out);
|
||||
void Dis_FromHiloTransfer(MIPSOpcode op, char *out);
|
||||
void Dis_JumpType(MIPSOpcode op, char *out);
|
||||
void Dis_JumpRegType(MIPSOpcode op, char *out);
|
||||
|
||||
void Dis_Allegrex(u32 op, char *out);
|
||||
void Dis_Allegrex2(u32 op, char *out);
|
||||
void Dis_Allegrex(MIPSOpcode op, char *out);
|
||||
void Dis_Allegrex2(MIPSOpcode op, char *out);
|
||||
|
||||
void Dis_Emuhack(u32 op, char *out);
|
||||
void Dis_Emuhack(MIPSOpcode op, char *out);
|
||||
}
|
||||
|
||||
@ -82,7 +82,7 @@ inline const char *MN(int v, MatrixSize size)
|
||||
return GetMatrixNotation(v, size);
|
||||
}
|
||||
|
||||
inline const char *VSuff(u32 op)
|
||||
inline const char *VSuff(MIPSOpcode op)
|
||||
{
|
||||
int a = (op>>7)&1;
|
||||
int b = (op>>15)&1;
|
||||
@ -99,7 +99,7 @@ inline const char *VSuff(u32 op)
|
||||
|
||||
namespace MIPSDis
|
||||
{
|
||||
void Dis_SV(u32 op, char *out)
|
||||
void Dis_SV(MIPSOpcode op, char *out)
|
||||
{
|
||||
int offset = (signed short)(op&0xFFFC);
|
||||
int vt = ((op>>16)&0x1f)|((op&3)<<5);
|
||||
@ -108,7 +108,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s\t%s, %d(%s)",name,VN(vt, V_Single),offset,RN(rs));
|
||||
}
|
||||
|
||||
void Dis_SVQ(u32 op, char *out)
|
||||
void Dis_SVQ(MIPSOpcode op, char *out)
|
||||
{
|
||||
int offset = (signed short)(op&0xFFFC);
|
||||
int vt = (((op>>16)&0x1f))|((op&1)<<5);
|
||||
@ -119,7 +119,7 @@ namespace MIPSDis
|
||||
strcat(out, ", wb");
|
||||
}
|
||||
|
||||
void Dis_SVLRQ(u32 op, char *out)
|
||||
void Dis_SVLRQ(MIPSOpcode op, char *out)
|
||||
{
|
||||
int offset = (signed short)(op&0xFFFC);
|
||||
int vt = (((op>>16)&0x1f))|((op&1)<<5);
|
||||
@ -129,7 +129,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s.q\t%s, %d(%s)",name,lr?"r":"l",VN(vt,V_Quad),offset,RN(rs));
|
||||
}
|
||||
|
||||
void Dis_Mftv(u32 op, char *out)
|
||||
void Dis_Mftv(MIPSOpcode op, char *out)
|
||||
{
|
||||
int vr = op & 0xFF;
|
||||
int rt = _RT;
|
||||
@ -137,7 +137,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s",name,vr>127?"c":"", RN(rt), VN(vr, V_Single));
|
||||
}
|
||||
|
||||
void Dis_VPFXST(u32 op, char *out)
|
||||
void Dis_VPFXST(MIPSOpcode op, char *out)
|
||||
{
|
||||
int data = op & 0xFFFFF;
|
||||
const char *name = MIPSGetName(op);
|
||||
@ -170,7 +170,7 @@ namespace MIPSDis
|
||||
}
|
||||
}
|
||||
|
||||
void Dis_VPFXD(u32 op, char *out)
|
||||
void Dis_VPFXD(MIPSOpcode op, char *out)
|
||||
{
|
||||
int data = op & 0xFFFFF;
|
||||
const char *name = MIPSGetName(op);
|
||||
@ -189,7 +189,7 @@ namespace MIPSDis
|
||||
}
|
||||
|
||||
|
||||
void Dis_Viim(u32 op, char *out)
|
||||
void Dis_Viim(MIPSOpcode op, char *out)
|
||||
{
|
||||
int vt = _VT;
|
||||
int imm = op&0xFFFF;
|
||||
@ -205,7 +205,7 @@ namespace MIPSDis
|
||||
sprintf(out, "ARGH");
|
||||
}
|
||||
|
||||
void Dis_Vcst(u32 op, char *out)
|
||||
void Dis_Vcst(MIPSOpcode op, char *out)
|
||||
{
|
||||
int conNum = (op>>16) & 0x1f;
|
||||
int vd = _VD;
|
||||
@ -239,14 +239,14 @@ namespace MIPSDis
|
||||
}
|
||||
|
||||
|
||||
void Dis_MatrixSet1(u32 op, char *out)
|
||||
void Dis_MatrixSet1(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
MatrixSize sz = GetMtxSize(op);
|
||||
sprintf(out, "%s%s\t%s",name,VSuff(op),MN(vd, sz));
|
||||
}
|
||||
void Dis_MatrixSet2(u32 op, char *out)
|
||||
void Dis_MatrixSet2(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
@ -254,7 +254,7 @@ namespace MIPSDis
|
||||
MatrixSize sz = GetMtxSize(op);
|
||||
sprintf(out, "%s%s\t%s, %s",name,VSuff(op),MN(vd, sz),MN(vs,sz));
|
||||
}
|
||||
void Dis_MatrixSet3(u32 op, char *out)
|
||||
void Dis_MatrixSet3(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
@ -264,7 +264,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s, %s",name,VSuff(op),MN(vd, sz),MN(vs,sz),MN(vt,sz));
|
||||
}
|
||||
|
||||
void Dis_MatrixMult(u32 op, char *out)
|
||||
void Dis_MatrixMult(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
@ -274,7 +274,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s, %s",name,VSuff(op),MN(vd, sz),MN(Xpose(vs),sz),MN(vt,sz));
|
||||
}
|
||||
|
||||
void Dis_VectorDot(u32 op, char *out)
|
||||
void Dis_VectorDot(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
@ -284,7 +284,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), VN(vd, V_Single), VN(vs,sz), VN(vt, sz));
|
||||
}
|
||||
|
||||
void Dis_Vtfm(u32 op, char *out)
|
||||
void Dis_Vtfm(MIPSOpcode op, char *out)
|
||||
{
|
||||
int vd = _VD;
|
||||
int vs = _VS;
|
||||
@ -309,12 +309,12 @@ namespace MIPSDis
|
||||
}
|
||||
}
|
||||
|
||||
void Dis_Vflush(u32 op, char *out)
|
||||
void Dis_Vflush(MIPSOpcode op, char *out)
|
||||
{
|
||||
sprintf(out,"vflush");
|
||||
}
|
||||
|
||||
void Dis_Vcrs(u32 op, char *out)
|
||||
void Dis_Vcrs(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vt = _VT;
|
||||
@ -330,7 +330,7 @@ namespace MIPSDis
|
||||
}
|
||||
|
||||
|
||||
void Dis_Vcmp(u32 op, char *out)
|
||||
void Dis_Vcmp(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vt = _VT;
|
||||
@ -341,7 +341,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), condNames[cond], VN(vs, sz), VN(vt,sz));
|
||||
}
|
||||
|
||||
void Dis_Vcmov(u32 op, char *out)
|
||||
void Dis_Vcmov(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
VectorSize sz = GetVecSize(op);
|
||||
@ -361,7 +361,7 @@ namespace MIPSDis
|
||||
|
||||
}
|
||||
|
||||
void Dis_Vfad(u32 op, char *out)
|
||||
void Dis_Vfad(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
@ -370,7 +370,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s", name, VSuff(op), VN(vd, V_Single), VN(vs,sz));
|
||||
}
|
||||
|
||||
void Dis_VScl(u32 op, char *out)
|
||||
void Dis_VScl(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
@ -380,14 +380,14 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), VN(vd, sz), VN(vs,sz), VN(vt, V_Single));
|
||||
}
|
||||
|
||||
void Dis_VectorSet1(u32 op, char *out)
|
||||
void Dis_VectorSet1(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
VectorSize sz = GetVecSize(op);
|
||||
sprintf(out, "%s%s\t%s",name,VSuff(op),VN(vd, sz));
|
||||
}
|
||||
void Dis_VectorSet2(u32 op, char *out)
|
||||
void Dis_VectorSet2(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
@ -395,7 +395,7 @@ namespace MIPSDis
|
||||
VectorSize sz = GetVecSize(op);
|
||||
sprintf(out, "%s%s\t%s, %s",name,VSuff(op),VN(vd, sz),VN(vs, sz));
|
||||
}
|
||||
void Dis_VectorSet3(u32 op, char *out)
|
||||
void Dis_VectorSet3(MIPSOpcode op, char *out)
|
||||
{
|
||||
const char *name = MIPSGetName(op);
|
||||
int vd = _VD;
|
||||
@ -405,7 +405,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), VN(vd, sz), VN(vs,sz), VN(vt, sz));
|
||||
}
|
||||
|
||||
void Dis_VRot(u32 op, char *out)
|
||||
void Dis_VRot(MIPSOpcode op, char *out)
|
||||
{
|
||||
int vd = _VD;
|
||||
int vs = _VS;
|
||||
@ -439,7 +439,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s, %s",name,VSuff(op),VN(vd, sz),VN(vs, V_Single),temp);
|
||||
}
|
||||
|
||||
void Dis_CrossQuat(u32 op, char *out)
|
||||
void Dis_CrossQuat(MIPSOpcode op, char *out)
|
||||
{
|
||||
VectorSize sz = GetVecSize(op);
|
||||
const char *name;
|
||||
@ -464,7 +464,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), VN(vd, sz), VN(vs,sz), VN(vt, sz));
|
||||
}
|
||||
|
||||
void Dis_Vbfy(u32 op, char *out)
|
||||
void Dis_Vbfy(MIPSOpcode op, char *out)
|
||||
{
|
||||
VectorSize sz = GetVecSize(op);
|
||||
int vd = _VD;
|
||||
@ -473,7 +473,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s",name,VSuff(op),VN(vd, sz),VN(vs, sz));
|
||||
}
|
||||
|
||||
void Dis_Vf2i(u32 op, char *out)
|
||||
void Dis_Vf2i(MIPSOpcode op, char *out)
|
||||
{
|
||||
VectorSize sz = GetVecSize(op);
|
||||
int vd = _VD;
|
||||
@ -483,7 +483,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s, %i",name,VSuff(op),VN(vd, sz),VN(vs, sz),imm);
|
||||
}
|
||||
|
||||
void Dis_Vs2i(u32 op, char *out)
|
||||
void Dis_Vs2i(MIPSOpcode op, char *out)
|
||||
{
|
||||
VectorSize sz = GetVecSize(op);
|
||||
int vd = _VD;
|
||||
@ -492,7 +492,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s",name,VSuff(op),VN(vd, sz),VN(vs, sz));
|
||||
}
|
||||
|
||||
void Dis_Vi2x(u32 op, char *out)
|
||||
void Dis_Vi2x(MIPSOpcode op, char *out)
|
||||
{
|
||||
VectorSize sz = GetVecSize(op);
|
||||
VectorSize dsz = GetHalfVectorSize(sz);
|
||||
@ -505,7 +505,7 @@ namespace MIPSDis
|
||||
sprintf(out, "%s%s\t%s, %s",name,VSuff(op),VN(vd, dsz),VN(vs, sz));
|
||||
}
|
||||
|
||||
void Dis_VBranch(u32 op, char *out)
|
||||
void Dis_VBranch(MIPSOpcode op, char *out)
|
||||
{
|
||||
u32 off = disPC;
|
||||
int imm = (signed short)(op&0xFFFF)<<2;
|
||||
|
||||
@ -23,38 +23,38 @@ extern u32 disPC;
|
||||
|
||||
namespace MIPSDis
|
||||
{
|
||||
void Dis_Mftv(u32 op, char *out);
|
||||
void Dis_Mftv(MIPSOpcode op, char *out);
|
||||
|
||||
void Dis_SV(u32 op, char *out);
|
||||
void Dis_SVQ(u32 op, char *out);
|
||||
void Dis_SVLRQ(u32 op, char *out);
|
||||
void Dis_SV(MIPSOpcode op, char *out);
|
||||
void Dis_SVQ(MIPSOpcode op, char *out);
|
||||
void Dis_SVLRQ(MIPSOpcode op, char *out);
|
||||
|
||||
void Dis_MatrixSet1(u32 op, char *out);
|
||||
void Dis_MatrixSet2(u32 op, char *out);
|
||||
void Dis_MatrixSet3(u32 op, char *out);
|
||||
void Dis_MatrixMult(u32 op, char *out);
|
||||
void Dis_MatrixSet1(MIPSOpcode op, char *out);
|
||||
void Dis_MatrixSet2(MIPSOpcode op, char *out);
|
||||
void Dis_MatrixSet3(MIPSOpcode op, char *out);
|
||||
void Dis_MatrixMult(MIPSOpcode op, char *out);
|
||||
|
||||
void Dis_VectorDot(u32 op, char *out);
|
||||
void Dis_Vfad(u32 op, char *out);
|
||||
void Dis_VectorSet1(u32 op, char *out);
|
||||
void Dis_VectorSet2(u32 op, char *out);
|
||||
void Dis_VectorSet3(u32 op, char *out);
|
||||
void Dis_VRot(u32 op, char *out);
|
||||
void Dis_VScl(u32 op, char *out);
|
||||
void Dis_VectorDot(MIPSOpcode op, char *out);
|
||||
void Dis_Vfad(MIPSOpcode op, char *out);
|
||||
void Dis_VectorSet1(MIPSOpcode op, char *out);
|
||||
void Dis_VectorSet2(MIPSOpcode op, char *out);
|
||||
void Dis_VectorSet3(MIPSOpcode op, char *out);
|
||||
void Dis_VRot(MIPSOpcode op, char *out);
|
||||
void Dis_VScl(MIPSOpcode op, char *out);
|
||||
|
||||
void Dis_VPFXST(u32 op, char *out);
|
||||
void Dis_VPFXD(u32 op, char *out);
|
||||
void Dis_Vcrs(u32 op, char *out);
|
||||
void Dis_Viim(u32 op, char *out);
|
||||
void Dis_Vcst(u32 op, char *out);
|
||||
void Dis_CrossQuat(u32 op, char *out);
|
||||
void Dis_Vtfm(u32 op, char *out);
|
||||
void Dis_Vcmp(u32 op, char *out);
|
||||
void Dis_Vcmov(u32 op, char *out);
|
||||
void Dis_Vflush(u32 op, char *out);
|
||||
void Dis_Vbfy(u32 op, char *out);
|
||||
void Dis_Vf2i(u32 op, char *out);
|
||||
void Dis_Vi2x(u32 op, char *out);
|
||||
void Dis_Vs2i(u32 op, char *out);
|
||||
void Dis_VBranch(u32 op, char *out);
|
||||
void Dis_VPFXST(MIPSOpcode op, char *out);
|
||||
void Dis_VPFXD(MIPSOpcode op, char *out);
|
||||
void Dis_Vcrs(MIPSOpcode op, char *out);
|
||||
void Dis_Viim(MIPSOpcode op, char *out);
|
||||
void Dis_Vcst(MIPSOpcode op, char *out);
|
||||
void Dis_CrossQuat(MIPSOpcode op, char *out);
|
||||
void Dis_Vtfm(MIPSOpcode op, char *out);
|
||||
void Dis_Vcmp(MIPSOpcode op, char *out);
|
||||
void Dis_Vcmov(MIPSOpcode op, char *out);
|
||||
void Dis_Vflush(MIPSOpcode op, char *out);
|
||||
void Dis_Vbfy(MIPSOpcode op, char *out);
|
||||
void Dis_Vf2i(MIPSOpcode op, char *out);
|
||||
void Dis_Vi2x(MIPSOpcode op, char *out);
|
||||
void Dis_Vs2i(MIPSOpcode op, char *out);
|
||||
void Dis_VBranch(MIPSOpcode op, char *out);
|
||||
}
|
||||
|
||||
@ -66,13 +66,13 @@ static inline void SkipLikely()
|
||||
int MIPS_SingleStep()
|
||||
{
|
||||
#if defined(ARM)
|
||||
u32 op = Memory::ReadUnchecked_U32(mipsr4k.pc);
|
||||
MIPSOpcode op = MIPSOpcode(Memory::ReadUnchecked_U32(mipsr4k.pc));
|
||||
#else
|
||||
u32 op = Memory::Read_Opcode_JIT(mipsr4k.pc);
|
||||
MIPSOpcode op = Memory::Read_Opcode_JIT(mipsr4k.pc);
|
||||
#endif
|
||||
/*
|
||||
// Choke on VFPU
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if (info & IS_VFPU)
|
||||
{
|
||||
if (!Core_IsStepping() && !GetAsyncKeyState(VK_LSHIFT))
|
||||
@ -117,7 +117,7 @@ void MIPS_ClearDelaySlot()
|
||||
|
||||
namespace MIPSInt
|
||||
{
|
||||
void Int_Cache(u32 op)
|
||||
void Int_Cache(MIPSOpcode op)
|
||||
{
|
||||
int imm = (s16)(op & 0xFFFF);
|
||||
int rs = _RS;
|
||||
@ -145,7 +145,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Syscall(u32 op)
|
||||
void Int_Syscall(MIPSOpcode op)
|
||||
{
|
||||
// Need to pre-move PC, as CallSyscall may result in a rescheduling!
|
||||
// To do this neater, we'll need a little generated kernel loop that syscall can jump to and then RFI from
|
||||
@ -162,13 +162,13 @@ namespace MIPSInt
|
||||
CallSyscall(op);
|
||||
}
|
||||
|
||||
void Int_Sync(u32 op)
|
||||
void Int_Sync(MIPSOpcode op)
|
||||
{
|
||||
//DEBUG_LOG(CPU, "sync");
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Break(u32 op)
|
||||
void Int_Break(MIPSOpcode op)
|
||||
{
|
||||
Reporting::ReportMessage("BREAK instruction hit");
|
||||
ERROR_LOG(CPU, "BREAK!");
|
||||
@ -177,7 +177,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_RelBranch(u32 op)
|
||||
void Int_RelBranch(MIPSOpcode op)
|
||||
{
|
||||
int imm = (signed short)(op&0xFFFF)<<2;
|
||||
int rs = _RS;
|
||||
@ -202,7 +202,7 @@ namespace MIPSInt
|
||||
}
|
||||
}
|
||||
|
||||
void Int_RelBranchRI(u32 op)
|
||||
void Int_RelBranchRI(MIPSOpcode op)
|
||||
{
|
||||
int imm = (signed short)(op&0xFFFF)<<2;
|
||||
int rs = _RS;
|
||||
@ -225,7 +225,7 @@ namespace MIPSInt
|
||||
}
|
||||
|
||||
|
||||
void Int_VBranch(u32 op)
|
||||
void Int_VBranch(MIPSOpcode op)
|
||||
{
|
||||
int imm = (signed short)(op&0xFFFF)<<2;
|
||||
u32 addr = PC + imm + 4;
|
||||
@ -243,7 +243,7 @@ namespace MIPSInt
|
||||
}
|
||||
}
|
||||
|
||||
void Int_FPUBranch(u32 op)
|
||||
void Int_FPUBranch(MIPSOpcode op)
|
||||
{
|
||||
int imm = (signed short)(op&0xFFFF)<<2;
|
||||
u32 addr = PC + imm + 4;
|
||||
@ -259,7 +259,7 @@ namespace MIPSInt
|
||||
}
|
||||
}
|
||||
|
||||
void Int_JumpType(u32 op)
|
||||
void Int_JumpType(MIPSOpcode op)
|
||||
{
|
||||
if (mipsr4k.inDelaySlot)
|
||||
_dbg_assert_msg_(CPU,0,"Jump in delay slot :(");
|
||||
@ -280,7 +280,7 @@ namespace MIPSInt
|
||||
}
|
||||
}
|
||||
|
||||
void Int_JumpRegType(u32 op)
|
||||
void Int_JumpRegType(MIPSOpcode op)
|
||||
{
|
||||
if (mipsr4k.inDelaySlot)
|
||||
{
|
||||
@ -306,7 +306,7 @@ namespace MIPSInt
|
||||
}
|
||||
}
|
||||
|
||||
void Int_IType(u32 op)
|
||||
void Int_IType(MIPSOpcode op)
|
||||
{
|
||||
s32 simm = (s32)(s16)(op & 0xFFFF);
|
||||
u32 uimm = (u32)(u16)(op & 0xFFFF);
|
||||
@ -338,7 +338,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_StoreSync(u32 op)
|
||||
void Int_StoreSync(MIPSOpcode op)
|
||||
{
|
||||
int imm = (signed short)(op&0xFFFF);
|
||||
int rt = _RT;
|
||||
@ -371,7 +371,7 @@ namespace MIPSInt
|
||||
}
|
||||
|
||||
|
||||
void Int_RType3(u32 op)
|
||||
void Int_RType3(MIPSOpcode op)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rs = _RS;
|
||||
@ -419,7 +419,7 @@ namespace MIPSInt
|
||||
}
|
||||
|
||||
|
||||
void Int_ITypeMem(u32 op)
|
||||
void Int_ITypeMem(MIPSOpcode op)
|
||||
{
|
||||
int imm = (signed short)(op&0xFFFF);
|
||||
int rt = _RT;
|
||||
@ -489,7 +489,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_FPULS(u32 op)
|
||||
void Int_FPULS(MIPSOpcode op)
|
||||
{
|
||||
s32 offset = (s16)(op&0xFFFF);
|
||||
int ft = _FT;
|
||||
@ -507,7 +507,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_mxc1(u32 op)
|
||||
void Int_mxc1(MIPSOpcode op)
|
||||
{
|
||||
int fs = _FS;
|
||||
int rt = _RT;
|
||||
@ -526,7 +526,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_RType2(u32 op)
|
||||
void Int_RType2(MIPSOpcode op)
|
||||
{
|
||||
int rs = _RS;
|
||||
int rd = _RD;
|
||||
@ -571,7 +571,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_MulDivType(u32 op)
|
||||
void Int_MulDivType(MIPSOpcode op)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rs = _RS;
|
||||
@ -674,7 +674,7 @@ namespace MIPSInt
|
||||
}
|
||||
|
||||
|
||||
void Int_ShiftType(u32 op)
|
||||
void Int_ShiftType(MIPSOpcode op)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rs = _RS;
|
||||
@ -728,7 +728,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Allegrex(u32 op)
|
||||
void Int_Allegrex(MIPSOpcode op)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rd = _RD;
|
||||
@ -771,7 +771,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Allegrex2(u32 op)
|
||||
void Int_Allegrex2(MIPSOpcode op)
|
||||
{
|
||||
int rt = _RT;
|
||||
int rd = _RD;
|
||||
@ -798,7 +798,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Special3(u32 op)
|
||||
void Int_Special3(MIPSOpcode op)
|
||||
{
|
||||
int rs = _RS;
|
||||
int rt = _RT;
|
||||
@ -832,7 +832,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_FPU2op(u32 op)
|
||||
void Int_FPU2op(MIPSOpcode op)
|
||||
{
|
||||
int fs = _FS;
|
||||
int fd = _FD;
|
||||
@ -865,7 +865,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_FPUComp(u32 op)
|
||||
void Int_FPUComp(MIPSOpcode op)
|
||||
{
|
||||
int fs = _FS;
|
||||
int ft = _FT;
|
||||
@ -921,7 +921,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_FPU3op(u32 op)
|
||||
void Int_FPU3op(MIPSOpcode op)
|
||||
{
|
||||
int ft = _FT;
|
||||
int fs = _FS;
|
||||
@ -940,7 +940,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Interrupt(u32 op)
|
||||
void Int_Interrupt(MIPSOpcode op)
|
||||
{
|
||||
static int reported = 0;
|
||||
switch (op & 1)
|
||||
@ -957,7 +957,7 @@ namespace MIPSInt
|
||||
}
|
||||
|
||||
|
||||
void Int_Emuhack(u32 op)
|
||||
void Int_Emuhack(MIPSOpcode op)
|
||||
{
|
||||
_dbg_assert_msg_(CPU,0,"Trying to interpret emuhack instruction that can't be interpreted");
|
||||
}
|
||||
|
||||
@ -25,33 +25,33 @@ int MIPS_SingleStep();
|
||||
|
||||
namespace MIPSInt
|
||||
{
|
||||
void Int_Unknown(u32 op);
|
||||
void Int_Unimpl(u32 op);
|
||||
void Int_Syscall(u32 op);
|
||||
void Int_Unknown(MIPSOpcode op);
|
||||
void Int_Unimpl(MIPSOpcode op);
|
||||
void Int_Syscall(MIPSOpcode op);
|
||||
|
||||
void Int_mxc1(u32 op);
|
||||
void Int_RelBranch(u32 op);
|
||||
void Int_RelBranchRI(u32 op);
|
||||
void Int_IType(u32 op);
|
||||
void Int_ITypeMem(u32 op);
|
||||
void Int_RType2(u32 op);
|
||||
void Int_RType3(u32 op);
|
||||
void Int_ShiftType(u32 op);
|
||||
void Int_MulDivType(u32 op);
|
||||
void Int_JumpType(u32 op);
|
||||
void Int_JumpRegType(u32 op);
|
||||
void Int_Allegrex2(u32 op);
|
||||
void Int_FPULS(u32 op);
|
||||
void Int_FPU3op(u32 op);
|
||||
void Int_FPU2op(u32 op);
|
||||
void Int_Allegrex(u32 op);
|
||||
void Int_FPUComp(u32 op);
|
||||
void Int_FPUBranch(u32 op);
|
||||
void Int_Emuhack(u32 op);
|
||||
void Int_Special3(u32 op);
|
||||
void Int_Interrupt(u32 op);
|
||||
void Int_Cache(u32 op);
|
||||
void Int_Sync(u32 op);
|
||||
void Int_Break(u32 op);
|
||||
void Int_StoreSync(u32 op);
|
||||
void Int_mxc1(MIPSOpcode op);
|
||||
void Int_RelBranch(MIPSOpcode op);
|
||||
void Int_RelBranchRI(MIPSOpcode op);
|
||||
void Int_IType(MIPSOpcode op);
|
||||
void Int_ITypeMem(MIPSOpcode op);
|
||||
void Int_RType2(MIPSOpcode op);
|
||||
void Int_RType3(MIPSOpcode op);
|
||||
void Int_ShiftType(MIPSOpcode op);
|
||||
void Int_MulDivType(MIPSOpcode op);
|
||||
void Int_JumpType(MIPSOpcode op);
|
||||
void Int_JumpRegType(MIPSOpcode op);
|
||||
void Int_Allegrex2(MIPSOpcode op);
|
||||
void Int_FPULS(MIPSOpcode op);
|
||||
void Int_FPU3op(MIPSOpcode op);
|
||||
void Int_FPU2op(MIPSOpcode op);
|
||||
void Int_Allegrex(MIPSOpcode op);
|
||||
void Int_FPUComp(MIPSOpcode op);
|
||||
void Int_FPUBranch(MIPSOpcode op);
|
||||
void Int_Emuhack(MIPSOpcode op);
|
||||
void Int_Special3(MIPSOpcode op);
|
||||
void Int_Interrupt(MIPSOpcode op);
|
||||
void Int_Cache(MIPSOpcode op);
|
||||
void Int_Sync(MIPSOpcode op);
|
||||
void Int_Break(MIPSOpcode op);
|
||||
void Int_StoreSync(MIPSOpcode op);
|
||||
}
|
||||
|
||||
@ -196,7 +196,7 @@ void EatPrefixes()
|
||||
|
||||
namespace MIPSInt
|
||||
{
|
||||
void Int_VPFX(u32 op)
|
||||
void Int_VPFX(MIPSOpcode op)
|
||||
{
|
||||
int data = op & 0xFFFFF;
|
||||
int regnum = (op >> 24) & 3;
|
||||
@ -204,7 +204,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_SVQ(u32 op)
|
||||
void Int_SVQ(MIPSOpcode op)
|
||||
{
|
||||
int imm = (signed short)(op&0xFFFC);
|
||||
int rs = _RS;
|
||||
@ -315,7 +315,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_VMatrixInit(u32 op)
|
||||
void Int_VMatrixInit(MIPSOpcode op)
|
||||
{
|
||||
static const float idt[16] =
|
||||
{
|
||||
@ -359,7 +359,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_VVectorInit(u32 op)
|
||||
void Int_VVectorInit(MIPSOpcode op)
|
||||
{
|
||||
int vd = _VD;
|
||||
VectorSize sz = GetVecSize(op);
|
||||
@ -387,7 +387,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Viim(u32 op)
|
||||
void Int_Viim(MIPSOpcode op)
|
||||
{
|
||||
int vt = _VT;
|
||||
s32 imm = (s16)(op&0xFFFF);
|
||||
@ -408,7 +408,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vidt(u32 op)
|
||||
void Int_Vidt(MIPSOpcode op)
|
||||
{
|
||||
int vd = _VD;
|
||||
VectorSize sz = GetVecSize(op);
|
||||
@ -435,7 +435,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
// The test really needs some work.
|
||||
void Int_Vmmul(u32 op)
|
||||
void Int_Vmmul(MIPSOpcode op)
|
||||
{
|
||||
float s[16];
|
||||
float t[16];
|
||||
@ -468,7 +468,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vmscl(u32 op)
|
||||
void Int_Vmscl(MIPSOpcode op)
|
||||
{
|
||||
float d[16];
|
||||
float s[16];
|
||||
@ -496,7 +496,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vmmov(u32 op)
|
||||
void Int_Vmmov(MIPSOpcode op)
|
||||
{
|
||||
float s[16];
|
||||
int vd = _VD;
|
||||
@ -509,13 +509,13 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vflush(u32 op)
|
||||
void Int_Vflush(MIPSOpcode op)
|
||||
{
|
||||
// DEBUG_LOG(CPU,"vflush");
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_VV2Op(u32 op)
|
||||
void Int_VV2Op(MIPSOpcode op)
|
||||
{
|
||||
float s[4], d[4];
|
||||
int vd = _VD;
|
||||
@ -555,7 +555,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vocp(u32 op)
|
||||
void Int_Vocp(MIPSOpcode op)
|
||||
{
|
||||
float s[4], d[4];
|
||||
int vd = _VD;
|
||||
@ -573,7 +573,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vsocp(u32 op)
|
||||
void Int_Vsocp(MIPSOpcode op)
|
||||
{
|
||||
float s[4], d[4];
|
||||
int vd = _VD;
|
||||
@ -596,7 +596,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vsgn(u32 op)
|
||||
void Int_Vsgn(MIPSOpcode op)
|
||||
{
|
||||
float s[4], d[4];
|
||||
int vd = _VD;
|
||||
@ -627,7 +627,7 @@ namespace MIPSInt
|
||||
return (int)round_ieee_754(param);
|
||||
}
|
||||
|
||||
void Int_Vf2i(u32 op) {
|
||||
void Int_Vf2i(MIPSOpcode op) {
|
||||
float s[4];
|
||||
int d[4];
|
||||
int vd = _VD;
|
||||
@ -665,7 +665,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vi2f(u32 op)
|
||||
void Int_Vi2f(MIPSOpcode op)
|
||||
{
|
||||
int s[4];
|
||||
float d[4];
|
||||
@ -686,7 +686,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vh2f(u32 op)
|
||||
void Int_Vh2f(MIPSOpcode op)
|
||||
{
|
||||
u32 s[4];
|
||||
float d[4];
|
||||
@ -721,7 +721,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vf2h(u32 op)
|
||||
void Int_Vf2h(MIPSOpcode op)
|
||||
{
|
||||
float s[4];
|
||||
u32 d[4];
|
||||
@ -753,7 +753,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vx2i(u32 op)
|
||||
void Int_Vx2i(MIPSOpcode op)
|
||||
{
|
||||
u32 s[4];
|
||||
u32 d[4] = {0};
|
||||
@ -845,7 +845,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vi2x(u32 op)
|
||||
void Int_Vi2x(MIPSOpcode op)
|
||||
{
|
||||
int s[4];
|
||||
u32 d[2] = {0};
|
||||
@ -920,7 +920,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_ColorConv(u32 op)
|
||||
void Int_ColorConv(MIPSOpcode op)
|
||||
{
|
||||
int vd = _VD;
|
||||
int vs = _VS;
|
||||
@ -969,7 +969,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_VDot(u32 op)
|
||||
void Int_VDot(MIPSOpcode op)
|
||||
{
|
||||
float s[4], t[4];
|
||||
float d;
|
||||
@ -994,7 +994,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_VHdp(u32 op)
|
||||
void Int_VHdp(MIPSOpcode op)
|
||||
{
|
||||
float s[4], t[4];
|
||||
float d;
|
||||
@ -1019,7 +1019,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vbfy(u32 op)
|
||||
void Int_Vbfy(MIPSOpcode op)
|
||||
{
|
||||
float s[4];
|
||||
float d[4];
|
||||
@ -1051,7 +1051,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vsrt1(u32 op)
|
||||
void Int_Vsrt1(MIPSOpcode op)
|
||||
{
|
||||
float s[4];
|
||||
float d[4];
|
||||
@ -1074,7 +1074,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vsrt2(u32 op)
|
||||
void Int_Vsrt2(MIPSOpcode op)
|
||||
{
|
||||
float s[4];
|
||||
float d[4];
|
||||
@ -1097,7 +1097,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vsrt3(u32 op)
|
||||
void Int_Vsrt3(MIPSOpcode op)
|
||||
{
|
||||
float s[4];
|
||||
float d[4];
|
||||
@ -1120,7 +1120,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vsrt4(u32 op)
|
||||
void Int_Vsrt4(MIPSOpcode op)
|
||||
{
|
||||
float s[4];
|
||||
float d[4];
|
||||
@ -1143,7 +1143,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vcrs(u32 op)
|
||||
void Int_Vcrs(MIPSOpcode op)
|
||||
{
|
||||
//half a cross product
|
||||
float s[4], t[4];
|
||||
@ -1167,7 +1167,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vdet(u32 op)
|
||||
void Int_Vdet(MIPSOpcode op)
|
||||
{
|
||||
float s[4], t[4];
|
||||
float d[4];
|
||||
@ -1187,7 +1187,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vfad(u32 op)
|
||||
void Int_Vfad(MIPSOpcode op)
|
||||
{
|
||||
float s[4];
|
||||
float d;
|
||||
@ -1209,7 +1209,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vavg(u32 op)
|
||||
void Int_Vavg(MIPSOpcode op)
|
||||
{
|
||||
float s[4];
|
||||
float d;
|
||||
@ -1231,7 +1231,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_VScl(u32 op)
|
||||
void Int_VScl(MIPSOpcode op)
|
||||
{
|
||||
float s[4];
|
||||
float d[4];
|
||||
@ -1258,7 +1258,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vrnds(u32 op)
|
||||
void Int_Vrnds(MIPSOpcode op)
|
||||
{
|
||||
int vd = _VD;
|
||||
int seed = VI(vd);
|
||||
@ -1267,7 +1267,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_VrndX(u32 op)
|
||||
void Int_VrndX(MIPSOpcode op)
|
||||
{
|
||||
float d[4];
|
||||
int vd = _VD;
|
||||
@ -1290,7 +1290,7 @@ namespace MIPSInt
|
||||
}
|
||||
|
||||
// Generates one line of a rotation matrix around one of the three axes
|
||||
void Int_Vrot(u32 op)
|
||||
void Int_Vrot(MIPSOpcode op)
|
||||
{
|
||||
int vd = _VD;
|
||||
int vs = _VS;
|
||||
@ -1315,7 +1315,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vtfm(u32 op)
|
||||
void Int_Vtfm(MIPSOpcode op)
|
||||
{
|
||||
int vd = _VD;
|
||||
int vs = _VS;
|
||||
@ -1372,7 +1372,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_SV(u32 op)
|
||||
void Int_SV(MIPSOpcode op)
|
||||
{
|
||||
s32 imm = (signed short)(op&0xFFFC);
|
||||
int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5);
|
||||
@ -1395,7 +1395,7 @@ namespace MIPSInt
|
||||
}
|
||||
|
||||
|
||||
void Int_Mftv(u32 op)
|
||||
void Int_Mftv(MIPSOpcode op)
|
||||
{
|
||||
int imm = op & 0xFF;
|
||||
int rt = _RT;
|
||||
@ -1433,7 +1433,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Vmfvc(u32 op) {
|
||||
void Int_Vmfvc(MIPSOpcode op) {
|
||||
int vs = _VS;
|
||||
int imm = op & 0xFF;
|
||||
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
|
||||
@ -1442,7 +1442,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Vmtvc(u32 op) {
|
||||
void Int_Vmtvc(MIPSOpcode op) {
|
||||
int vs = _VS;
|
||||
int imm = op & 0xFF;
|
||||
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
|
||||
@ -1451,7 +1451,7 @@ namespace MIPSInt
|
||||
PC += 4;
|
||||
}
|
||||
|
||||
void Int_Vcst(u32 op)
|
||||
void Int_Vcst(MIPSOpcode op)
|
||||
{
|
||||
int conNum = (op >> 16) & 0x1f;
|
||||
int vd = _VD;
|
||||
@ -1465,7 +1465,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vcmp(u32 op)
|
||||
void Int_Vcmp(MIPSOpcode op)
|
||||
{
|
||||
int vs = _VS;
|
||||
int vt = _VT;
|
||||
@ -1527,7 +1527,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vminmax(u32 op) {
|
||||
void Int_Vminmax(MIPSOpcode op) {
|
||||
int vt = _VT;
|
||||
int vs = _VS;
|
||||
int vd = _VD;
|
||||
@ -1565,7 +1565,7 @@ namespace MIPSInt
|
||||
}
|
||||
|
||||
// This doesn't quite pass all the tests :/
|
||||
void Int_Vscmp(u32 op) {
|
||||
void Int_Vscmp(MIPSOpcode op) {
|
||||
int vt = _VT;
|
||||
int vs = _VS;
|
||||
int vd = _VD;
|
||||
@ -1588,7 +1588,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vsge(u32 op) {
|
||||
void Int_Vsge(MIPSOpcode op) {
|
||||
int vt = _VT;
|
||||
int vs = _VS;
|
||||
int vd = _VD;
|
||||
@ -1614,7 +1614,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vslt(u32 op) {
|
||||
void Int_Vslt(MIPSOpcode op) {
|
||||
int vt = _VT;
|
||||
int vs = _VS;
|
||||
int vd = _VD;
|
||||
@ -1641,7 +1641,7 @@ namespace MIPSInt
|
||||
}
|
||||
|
||||
|
||||
void Int_Vcmov(u32 op)
|
||||
void Int_Vcmov(MIPSOpcode op)
|
||||
{
|
||||
int vs = _VS;
|
||||
int vd = _VD;
|
||||
@ -1683,7 +1683,7 @@ namespace MIPSInt
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_VecDo3(u32 op)
|
||||
void Int_VecDo3(MIPSOpcode op)
|
||||
{
|
||||
int vd = _VD;
|
||||
int vs = _VS;
|
||||
@ -1729,7 +1729,7 @@ bad:
|
||||
}
|
||||
|
||||
|
||||
void Int_CrossQuat(u32 op)
|
||||
void Int_CrossQuat(MIPSOpcode op)
|
||||
{
|
||||
int vd = _VD;
|
||||
int vs = _VS;
|
||||
@ -1764,7 +1764,7 @@ bad:
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vlgb(u32 op)
|
||||
void Int_Vlgb(MIPSOpcode op)
|
||||
{
|
||||
// S & D valid
|
||||
Reporting::ReportMessage("vlgb not implemented");
|
||||
@ -1775,7 +1775,7 @@ bad:
|
||||
|
||||
// There has to be a concise way of expressing this in terms of
|
||||
// bit manipulation on the raw floats.
|
||||
void Int_Vwbn(u32 op) {
|
||||
void Int_Vwbn(MIPSOpcode op) {
|
||||
Reporting::ReportMessage("vwbn not implemented");
|
||||
_dbg_assert_msg_(CPU,0,"vwbn not implemented");
|
||||
PC += 4;
|
||||
@ -1807,7 +1807,7 @@ bad:
|
||||
EatPrefixes();*/
|
||||
}
|
||||
|
||||
void Int_Vsbn(u32 op)
|
||||
void Int_Vsbn(MIPSOpcode op)
|
||||
{
|
||||
Reporting::ReportMessage("vsbn not implemented");
|
||||
_dbg_assert_msg_(CPU,0,"vsbn not implemented");
|
||||
@ -1815,7 +1815,7 @@ bad:
|
||||
EatPrefixes();
|
||||
}
|
||||
|
||||
void Int_Vsbz(u32 op)
|
||||
void Int_Vsbz(MIPSOpcode op)
|
||||
{
|
||||
Reporting::ReportMessage("vsbz not implemented");
|
||||
_dbg_assert_msg_(CPU,0,"vsbz not implemented");
|
||||
|
||||
@ -25,60 +25,60 @@ int MIPS_SingleStep();
|
||||
|
||||
namespace MIPSInt
|
||||
{
|
||||
void Int_SV(u32 op);
|
||||
void Int_SVQ(u32 op);
|
||||
void Int_Mftv(u32 op);
|
||||
void Int_MatrixSet(u32 op);
|
||||
void Int_VecDo3(u32 op);
|
||||
void Int_Vcst(u32 op);
|
||||
void Int_VMatrixInit(u32 op);
|
||||
void Int_VVectorInit(u32 op);
|
||||
void Int_Vmmul(u32 op);
|
||||
void Int_Vmscl(u32 op);
|
||||
void Int_Vmmov(u32 op);
|
||||
void Int_VV2Op(u32 op);
|
||||
void Int_Vrot(u32 op);
|
||||
void Int_VDot(u32 op);
|
||||
void Int_VHdp(u32 op);
|
||||
void Int_Vavg(u32 op);
|
||||
void Int_Vfad(u32 op);
|
||||
void Int_Vocp(u32 op);
|
||||
void Int_Vsocp(u32 op);
|
||||
void Int_Vsgn(u32 op);
|
||||
void Int_Vtfm(u32 op);
|
||||
void Int_Viim(u32 op);
|
||||
void Int_VScl(u32 op);
|
||||
void Int_Vidt(u32 op);
|
||||
void Int_Vcmp(u32 op);
|
||||
void Int_Vminmax(u32 op);
|
||||
void Int_Vscmp(u32 op);
|
||||
void Int_Vcrs(u32 op);
|
||||
void Int_Vdet(u32 op);
|
||||
void Int_Vcmov(u32 op);
|
||||
void Int_CrossQuat(u32 op);
|
||||
void Int_VPFX(u32 op);
|
||||
void Int_Vflush(u32 op);
|
||||
void Int_Vbfy(u32 op);
|
||||
void Int_Vsrt1(u32 op);
|
||||
void Int_Vsrt2(u32 op);
|
||||
void Int_Vsrt3(u32 op);
|
||||
void Int_Vsrt4(u32 op);
|
||||
void Int_Vf2i(u32 op);
|
||||
void Int_Vi2f(u32 op);
|
||||
void Int_Vi2x(u32 op);
|
||||
void Int_Vx2i(u32 op);
|
||||
void Int_VBranch(u32 op);
|
||||
void Int_Vrnds(u32 op);
|
||||
void Int_VrndX(u32 op);
|
||||
void Int_ColorConv(u32 op);
|
||||
void Int_Vh2f(u32 op);
|
||||
void Int_Vf2h(u32 op);
|
||||
void Int_Vsge(u32 op);
|
||||
void Int_Vslt(u32 op);
|
||||
void Int_Vmfvc(u32 op);
|
||||
void Int_Vmtvc(u32 op);
|
||||
void Int_Vlgb(u32 op);
|
||||
void Int_Vwbn(u32 op);
|
||||
void Int_Vsbn(u32 op);
|
||||
void Int_Vsbz(u32 op);
|
||||
void Int_SV(MIPSOpcode op);
|
||||
void Int_SVQ(MIPSOpcode op);
|
||||
void Int_Mftv(MIPSOpcode op);
|
||||
void Int_MatrixSet(MIPSOpcode op);
|
||||
void Int_VecDo3(MIPSOpcode op);
|
||||
void Int_Vcst(MIPSOpcode op);
|
||||
void Int_VMatrixInit(MIPSOpcode op);
|
||||
void Int_VVectorInit(MIPSOpcode op);
|
||||
void Int_Vmmul(MIPSOpcode op);
|
||||
void Int_Vmscl(MIPSOpcode op);
|
||||
void Int_Vmmov(MIPSOpcode op);
|
||||
void Int_VV2Op(MIPSOpcode op);
|
||||
void Int_Vrot(MIPSOpcode op);
|
||||
void Int_VDot(MIPSOpcode op);
|
||||
void Int_VHdp(MIPSOpcode op);
|
||||
void Int_Vavg(MIPSOpcode op);
|
||||
void Int_Vfad(MIPSOpcode op);
|
||||
void Int_Vocp(MIPSOpcode op);
|
||||
void Int_Vsocp(MIPSOpcode op);
|
||||
void Int_Vsgn(MIPSOpcode op);
|
||||
void Int_Vtfm(MIPSOpcode op);
|
||||
void Int_Viim(MIPSOpcode op);
|
||||
void Int_VScl(MIPSOpcode op);
|
||||
void Int_Vidt(MIPSOpcode op);
|
||||
void Int_Vcmp(MIPSOpcode op);
|
||||
void Int_Vminmax(MIPSOpcode op);
|
||||
void Int_Vscmp(MIPSOpcode op);
|
||||
void Int_Vcrs(MIPSOpcode op);
|
||||
void Int_Vdet(MIPSOpcode op);
|
||||
void Int_Vcmov(MIPSOpcode op);
|
||||
void Int_CrossQuat(MIPSOpcode op);
|
||||
void Int_VPFX(MIPSOpcode op);
|
||||
void Int_Vflush(MIPSOpcode op);
|
||||
void Int_Vbfy(MIPSOpcode op);
|
||||
void Int_Vsrt1(MIPSOpcode op);
|
||||
void Int_Vsrt2(MIPSOpcode op);
|
||||
void Int_Vsrt3(MIPSOpcode op);
|
||||
void Int_Vsrt4(MIPSOpcode op);
|
||||
void Int_Vf2i(MIPSOpcode op);
|
||||
void Int_Vi2f(MIPSOpcode op);
|
||||
void Int_Vi2x(MIPSOpcode op);
|
||||
void Int_Vx2i(MIPSOpcode op);
|
||||
void Int_VBranch(MIPSOpcode op);
|
||||
void Int_Vrnds(MIPSOpcode op);
|
||||
void Int_VrndX(MIPSOpcode op);
|
||||
void Int_ColorConv(MIPSOpcode op);
|
||||
void Int_Vh2f(MIPSOpcode op);
|
||||
void Int_Vf2h(MIPSOpcode op);
|
||||
void Int_Vsge(MIPSOpcode op);
|
||||
void Int_Vslt(MIPSOpcode op);
|
||||
void Int_Vmfvc(MIPSOpcode op);
|
||||
void Int_Vmtvc(MIPSOpcode op);
|
||||
void Int_Vlgb(MIPSOpcode op);
|
||||
void Int_Vwbn(MIPSOpcode op);
|
||||
void Int_Vsbn(MIPSOpcode op);
|
||||
void Int_Vsbz(MIPSOpcode op);
|
||||
}
|
||||
@ -44,15 +44,15 @@ namespace MIPSStackWalk {
|
||||
return INVALIDTARGET;
|
||||
}
|
||||
|
||||
bool IsSWInstr(u32 op) {
|
||||
bool IsSWInstr(MIPSOpcode op) {
|
||||
return (op & MIPSTABLE_IMM_MASK) == 0xAC000000;
|
||||
}
|
||||
|
||||
bool IsAddImmInstr(u32 op) {
|
||||
bool IsAddImmInstr(MIPSOpcode op) {
|
||||
return (op & MIPSTABLE_IMM_MASK) == 0x20000000 || (op & MIPSTABLE_IMM_MASK) == 0x24000000;
|
||||
}
|
||||
|
||||
bool IsMovRegsInstr(u32 op) {
|
||||
bool IsMovRegsInstr(MIPSOpcode op) {
|
||||
// TODO: There are more options here. Let's assume addu for now.
|
||||
if ((op & MIPSTABLE_SPECIAL_MASK) == 0x00000021) {
|
||||
return _RS == 0 || _RT == 0;
|
||||
@ -67,7 +67,7 @@ namespace MIPSStackWalk {
|
||||
// It ought to be pretty close.
|
||||
u32 stop = pc - 32 * 4;
|
||||
for (; Memory::IsValidAddress(pc) && pc >= stop; pc -= 4) {
|
||||
u32 op = Memory::Read_Instruction(pc);
|
||||
MIPSOpcode op = Memory::Read_Instruction(pc);
|
||||
|
||||
// We're looking for a "mov fp, sp" close by a "addiu sp, sp, -N".
|
||||
if (IsMovRegsInstr(op) && _RD == MIPS_REG_FP && (_RS == MIPS_REG_SP || _RT == MIPS_REG_SP)) {
|
||||
@ -83,7 +83,7 @@ namespace MIPSStackWalk {
|
||||
int ra_offset = -1;
|
||||
u32 stop = entry == INVALIDTARGET ? 0 : entry;
|
||||
for (u32 pc = frame.pc; Memory::IsValidAddress(pc) && pc >= stop; pc -= 4) {
|
||||
u32 op = Memory::Read_Instruction(pc);
|
||||
MIPSOpcode op = Memory::Read_Instruction(pc);
|
||||
|
||||
// Here's where they store the ra address.
|
||||
if (IsSWInstr(op) && _RT == MIPS_REG_RA && _RS == MIPS_REG_SP) {
|
||||
|
||||
@ -71,7 +71,7 @@ struct MIPSInstruction
|
||||
#endif
|
||||
MIPSInterpretFunc interpret;
|
||||
//MIPSInstructionInfo information;
|
||||
u32 flags;
|
||||
MIPSInfo flags;
|
||||
};
|
||||
|
||||
#define INVALID {-2}
|
||||
@ -80,7 +80,7 @@ struct MIPSInstruction
|
||||
|
||||
#ifndef FINAL
|
||||
#define ENCODING(a) {a}
|
||||
#define INSTR(name, comp, dis, inter, flags) {-1, N(name), comp, dis, inter, flags}
|
||||
#define INSTR(name, comp, dis, inter, flags) {-1, N(name), comp, dis, inter, MIPSInfo(flags)}
|
||||
#else
|
||||
#define ENCODING(a) {a}
|
||||
#define INSTR(name, comp, dis, inter, flags) {-1, comp, inter, flags}
|
||||
@ -891,7 +891,7 @@ const MIPSInstruction *mipsTables[NumEncodings] =
|
||||
//Todo : generate dispatcher functions from above tables
|
||||
//instead of this horribly slow abomination
|
||||
|
||||
const MIPSInstruction *MIPSGetInstruction(u32 op)
|
||||
const MIPSInstruction *MIPSGetInstruction(MIPSOpcode op)
|
||||
{
|
||||
MipsEncoding encoding = Imme;
|
||||
const MIPSInstruction *instr = &tableImmediate[op>>26];
|
||||
@ -919,19 +919,19 @@ const MIPSInstruction *MIPSGetInstruction(u32 op)
|
||||
|
||||
|
||||
|
||||
void MIPSCompileOp(u32 op)
|
||||
void MIPSCompileOp(MIPSOpcode op)
|
||||
{
|
||||
if (op==0)
|
||||
return;
|
||||
const MIPSInstruction *instr = MIPSGetInstruction(op);
|
||||
const int info = MIPSGetInfo(op);
|
||||
const MIPSInfo info = MIPSGetInfo(op);
|
||||
if (instr)
|
||||
{
|
||||
if (instr->compile)
|
||||
(MIPSComp::jit->*(instr->compile))(op); // woohoo, member functions pointers!
|
||||
else
|
||||
{
|
||||
ERROR_LOG_REPORT(CPU,"MIPSCompileOp %08x failed",op);
|
||||
ERROR_LOG_REPORT(CPU,"MIPSCompileOp %08x failed",op.encoding);
|
||||
//MessageBox(0,"ARGH2",0,0);//compile an interpreter call
|
||||
}
|
||||
|
||||
@ -940,12 +940,12 @@ void MIPSCompileOp(u32 op)
|
||||
}
|
||||
else
|
||||
{
|
||||
ERROR_LOG_REPORT(CPU, "MIPSCompileOp: Invalid instruction %08x", op);
|
||||
ERROR_LOG_REPORT(CPU, "MIPSCompileOp: Invalid instruction %08x", op.encoding);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void MIPSDisAsm(u32 op, u32 pc, char *out, bool tabsToSpaces)
|
||||
void MIPSDisAsm(MIPSOpcode op, u32 pc, char *out, bool tabsToSpaces)
|
||||
{
|
||||
if (op == 0)
|
||||
{
|
||||
@ -973,7 +973,7 @@ void MIPSDisAsm(u32 op, u32 pc, char *out, bool tabsToSpaces)
|
||||
}
|
||||
|
||||
|
||||
void MIPSInterpret(u32 op) //only for those rare ones
|
||||
void MIPSInterpret(MIPSOpcode op) //only for those rare ones
|
||||
{
|
||||
//if ((op&0xFFFFF000) == 0xd0110000)
|
||||
// Crash();
|
||||
@ -986,7 +986,7 @@ void MIPSInterpret(u32 op) //only for those rare ones
|
||||
instr->interpret(op);
|
||||
else
|
||||
{
|
||||
ERROR_LOG_REPORT(CPU, "Unknown instruction %08x at %08x", op, currentMIPS->pc);
|
||||
ERROR_LOG_REPORT(CPU, "Unknown instruction %08x at %08x", op.encoding, currentMIPS->pc);
|
||||
// Try to disassemble it
|
||||
char disasm[256];
|
||||
MIPSDisAsm(op, currentMIPS->pc, disasm);
|
||||
@ -1014,11 +1014,11 @@ int MIPSInterpret_RunUntil(u64 globalTicks)
|
||||
// int cycles = 0;
|
||||
{
|
||||
again:
|
||||
u32 op = Memory::Read_U32(curMips->pc);
|
||||
//u32 op = Memory::Read_Opcode_JIT(mipsr4k.pc);
|
||||
MIPSOpcode op = MIPSOpcode(Memory::Read_U32(curMips->pc));
|
||||
//MIPSOpcode op = Memory::Read_Opcode_JIT(mipsr4k.pc);
|
||||
/*
|
||||
// Choke on VFPU
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if (info & IS_VFPU)
|
||||
{
|
||||
if (!Core_IsStepping() && !GetAsyncKeyState(VK_LSHIFT))
|
||||
@ -1079,7 +1079,7 @@ static inline void DelayBranchTo(MIPSState *curMips, u32 where)
|
||||
curMips->inDelaySlot = true;
|
||||
}
|
||||
|
||||
const char *MIPSGetName(u32 op)
|
||||
const char *MIPSGetName(MIPSOpcode op)
|
||||
{
|
||||
static const char *noname = "unk";
|
||||
const MIPSInstruction *instr = MIPSGetInstruction(op);
|
||||
@ -1089,17 +1089,17 @@ const char *MIPSGetName(u32 op)
|
||||
return instr->name;
|
||||
}
|
||||
|
||||
u32 MIPSGetInfo(u32 op)
|
||||
MIPSInfo MIPSGetInfo(MIPSOpcode op)
|
||||
{
|
||||
// int crunch = CRUNCH_MIPS_OP(op);
|
||||
const MIPSInstruction *instr = MIPSGetInstruction(op);
|
||||
if (instr)
|
||||
return instr->flags;
|
||||
else
|
||||
return 0;
|
||||
return MIPSInfo(BAD_INSTRUCTION);
|
||||
}
|
||||
|
||||
MIPSInterpretFunc MIPSGetInterpretFunc(u32 op)
|
||||
MIPSInterpretFunc MIPSGetInterpretFunc(MIPSOpcode op)
|
||||
{
|
||||
const MIPSInstruction *instr = MIPSGetInstruction(op);
|
||||
if (instr->interpret)
|
||||
@ -1109,9 +1109,9 @@ MIPSInterpretFunc MIPSGetInterpretFunc(u32 op)
|
||||
}
|
||||
|
||||
// TODO: Do something that makes sense here.
|
||||
int MIPSGetInstructionCycleEstimate(u32 op)
|
||||
int MIPSGetInstructionCycleEstimate(MIPSOpcode op)
|
||||
{
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
if (info & DELAYSLOT)
|
||||
return 2;
|
||||
else
|
||||
|
||||
@ -17,7 +17,23 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "../../Globals.h"
|
||||
#include "Globals.h"
|
||||
#include "Core/MIPS/MIPS.h"
|
||||
|
||||
struct MIPSInfo {
|
||||
MIPSInfo() {
|
||||
value = 0;
|
||||
}
|
||||
|
||||
explicit MIPSInfo(u32 v) : value(v) {
|
||||
}
|
||||
|
||||
u32 operator & (const u32 &arg) const {
|
||||
return value & arg;
|
||||
}
|
||||
|
||||
u32 value;
|
||||
};
|
||||
|
||||
#define CONDTYPE_MASK 0x00000007
|
||||
#define CONDTYPE_EQ 0x00000001
|
||||
@ -40,50 +56,49 @@
|
||||
#define IS_CONDMOVE 0x00000008
|
||||
#define DELAYSLOT 0x00000010
|
||||
#define BAD_INSTRUCTION 0x00000020
|
||||
#define UNCONDITIONAL 0x00000040
|
||||
#define LIKELY 0x00000080
|
||||
#define IS_CONDBRANCH 0x00000100
|
||||
#define IS_JUMP 0x00000200
|
||||
#define LIKELY 0x00000040
|
||||
#define IS_CONDBRANCH 0x00000080
|
||||
#define IS_JUMP 0x00000100
|
||||
|
||||
#define IN_RS 0x00000400
|
||||
#define IN_RS_ADDR (0x00000800 | IN_RS)
|
||||
#define IN_RS_SHIFT (0x00001000 | IN_RS)
|
||||
#define IN_RT 0x00002000
|
||||
#define IN_SA 0x00004000
|
||||
#define IN_IMM16 0x00008000
|
||||
#define IN_IMM26 0x00010000
|
||||
#define IN_MEM 0x00020000
|
||||
#define IN_OTHER 0x00040000
|
||||
#define IN_FPUFLAG 0x00080000
|
||||
#define IN_RS 0x00000200
|
||||
#define IN_RS_ADDR (0x00000400 | IN_RS)
|
||||
#define IN_RS_SHIFT (0x00000800 | IN_RS)
|
||||
#define IN_RT 0x00001000
|
||||
#define IN_SA 0x00002000
|
||||
#define IN_IMM16 0x00004000
|
||||
#define IN_IMM26 0x00008000
|
||||
#define IN_MEM 0x00010000
|
||||
#define IN_OTHER 0x00020000
|
||||
#define IN_FPUFLAG 0x00040000
|
||||
|
||||
#define OUT_RT 0x00100000
|
||||
#define OUT_RD 0x00200000
|
||||
#define OUT_RA 0x00400000
|
||||
#define OUT_MEM 0x00800000
|
||||
#define OUT_OTHER 0x01000000
|
||||
#define OUT_FPUFLAG 0x02000000
|
||||
#define OUT_EAT_PREFIX 0x04000000
|
||||
#define OUT_RT 0x00080000
|
||||
#define OUT_RD 0x00100000
|
||||
#define OUT_RA 0x00200000
|
||||
#define OUT_MEM 0x00400000
|
||||
#define OUT_OTHER 0x00800000
|
||||
#define OUT_FPUFLAG 0x01000000
|
||||
#define OUT_EAT_PREFIX 0x02000000
|
||||
|
||||
#define VFPU_NO_PREFIX 0x08000000
|
||||
#define IS_VFPU 0x80000000
|
||||
#define VFPU_NO_PREFIX 0x04000000
|
||||
#define IS_VFPU 0x08000000
|
||||
|
||||
#ifndef CDECL
|
||||
#define CDECL
|
||||
#endif
|
||||
|
||||
typedef void (CDECL *MIPSDisFunc)(u32 opcode, char *out);
|
||||
typedef void (CDECL *MIPSInterpretFunc)(u32 opcode);
|
||||
typedef void (CDECL *MIPSDisFunc)(MIPSOpcode opcode, char *out);
|
||||
typedef void (CDECL *MIPSInterpretFunc)(MIPSOpcode opcode);
|
||||
|
||||
|
||||
void MIPSCompileOp(u32 op);
|
||||
void MIPSDisAsm(u32 op, u32 pc, char *out, bool tabsToSpaces = false);
|
||||
u32 MIPSGetInfo(u32 op);
|
||||
void MIPSInterpret(u32 op); //only for those rare ones
|
||||
void MIPSCompileOp(MIPSOpcode op);
|
||||
void MIPSDisAsm(MIPSOpcode op, u32 pc, char *out, bool tabsToSpaces = false);
|
||||
MIPSInfo MIPSGetInfo(MIPSOpcode op);
|
||||
void MIPSInterpret(MIPSOpcode op); //only for those rare ones
|
||||
int MIPSInterpret_RunUntil(u64 globalTicks);
|
||||
MIPSInterpretFunc MIPSGetInterpretFunc(u32 op);
|
||||
MIPSInterpretFunc MIPSGetInterpretFunc(MIPSOpcode op);
|
||||
|
||||
int MIPSGetInstructionCycleEstimate(u32 op);
|
||||
const char *MIPSGetName(u32 op);
|
||||
int MIPSGetInstructionCycleEstimate(MIPSOpcode op);
|
||||
const char *MIPSGetName(MIPSOpcode op);
|
||||
|
||||
|
||||
void FillMIPSTables();
|
||||
|
||||
@ -226,7 +226,7 @@ VectorSize GetHalfVectorSize(VectorSize sz)
|
||||
}
|
||||
}
|
||||
|
||||
VectorSize GetVecSize(u32 op)
|
||||
VectorSize GetVecSize(MIPSOpcode op)
|
||||
{
|
||||
int a = (op>>7)&1;
|
||||
int b = (op>>15)&1;
|
||||
@ -241,7 +241,7 @@ VectorSize GetVecSize(u32 op)
|
||||
}
|
||||
}
|
||||
|
||||
MatrixSize GetMtxSize(u32 op)
|
||||
MatrixSize GetMtxSize(MIPSOpcode op)
|
||||
{
|
||||
int a = (op>>7)&1;
|
||||
int b = (op>>15)&1;
|
||||
|
||||
@ -65,8 +65,8 @@ inline int GetMtx(int matrixReg) {
|
||||
return (matrixReg >> 2) & 7;
|
||||
}
|
||||
|
||||
VectorSize GetVecSize(u32 op);
|
||||
MatrixSize GetMtxSize(u32 op);
|
||||
VectorSize GetVecSize(MIPSOpcode op);
|
||||
MatrixSize GetMtxSize(MIPSOpcode op);
|
||||
VectorSize GetHalfVectorSize(VectorSize sz);
|
||||
int GetNumVectorElements(VectorSize sz);
|
||||
int GetMatrixSide(MatrixSize sz);
|
||||
|
||||
@ -39,7 +39,7 @@ using namespace MIPSAnalyst;
|
||||
|
||||
namespace MIPSComp
|
||||
{
|
||||
void Jit::CompImmLogic(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &))
|
||||
void Jit::CompImmLogic(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &))
|
||||
{
|
||||
u32 uimm = (u16)(op & 0xFFFF);
|
||||
int rt = _RT;
|
||||
@ -52,7 +52,7 @@ namespace MIPSComp
|
||||
gpr.UnlockAll();
|
||||
}
|
||||
|
||||
void Jit::Comp_IType(u32 op)
|
||||
void Jit::Comp_IType(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension
|
||||
@ -159,7 +159,7 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_RType2(u32 op)
|
||||
void Jit::Comp_RType2(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int rs = _RS;
|
||||
@ -266,7 +266,7 @@ namespace MIPSComp
|
||||
}
|
||||
|
||||
//rd = rs X rt
|
||||
void Jit::CompTriArith(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &), u32 (*doImm)(const u32, const u32))
|
||||
void Jit::CompTriArith(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &), u32 (*doImm)(const u32, const u32))
|
||||
{
|
||||
int rt = _RT;
|
||||
int rs = _RS;
|
||||
@ -323,7 +323,7 @@ namespace MIPSComp
|
||||
gpr.UnlockAll();
|
||||
}
|
||||
|
||||
void Jit::Comp_RType3(u32 op)
|
||||
void Jit::Comp_RType3(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE
|
||||
|
||||
@ -507,7 +507,7 @@ namespace MIPSComp
|
||||
return (a >> sa) | (a << (32 - sa));
|
||||
}
|
||||
|
||||
void Jit::CompShiftImm(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32))
|
||||
void Jit::CompShiftImm(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32))
|
||||
{
|
||||
int rd = _RD;
|
||||
int rt = _RT;
|
||||
@ -528,7 +528,7 @@ namespace MIPSComp
|
||||
}
|
||||
|
||||
// "over-shifts" work the same as on x86 - only bottom 5 bits are used to get the shift value
|
||||
void Jit::CompShiftVar(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32))
|
||||
void Jit::CompShiftVar(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32))
|
||||
{
|
||||
int rd = _RD;
|
||||
int rt = _RT;
|
||||
@ -563,7 +563,7 @@ namespace MIPSComp
|
||||
gpr.UnlockAll();
|
||||
}
|
||||
|
||||
void Jit::Comp_ShiftType(u32 op)
|
||||
void Jit::Comp_ShiftType(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int rs = _RS;
|
||||
@ -591,7 +591,7 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_Special3(u32 op)
|
||||
void Jit::Comp_Special3(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int rs = _RS;
|
||||
@ -659,7 +659,7 @@ namespace MIPSComp
|
||||
}
|
||||
|
||||
|
||||
void Jit::Comp_Allegrex(u32 op)
|
||||
void Jit::Comp_Allegrex(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE
|
||||
int rt = _RT;
|
||||
@ -769,7 +769,7 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_Allegrex2(u32 op)
|
||||
void Jit::Comp_Allegrex2(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE
|
||||
int rt = _RT;
|
||||
@ -799,7 +799,7 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_MulDivType(u32 op)
|
||||
void Jit::Comp_MulDivType(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int rt = _RT;
|
||||
|
||||
@ -72,13 +72,13 @@ namespace MIPSComp
|
||||
static u32 intBranchExit;
|
||||
static u32 jitBranchExit;
|
||||
|
||||
static void JitBranchLog(u32 op, u32 pc)
|
||||
static void JitBranchLog(MIPSOpcode op, u32 pc)
|
||||
{
|
||||
currentMIPS->pc = pc;
|
||||
currentMIPS->inDelaySlot = false;
|
||||
|
||||
MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
func(op);
|
||||
|
||||
// Branch taken, use nextPC.
|
||||
@ -98,7 +98,7 @@ static void JitBranchLog(u32 op, u32 pc)
|
||||
currentMIPS->inDelaySlot = false;
|
||||
}
|
||||
|
||||
static void JitBranchLogMismatch(u32 op, u32 pc)
|
||||
static void JitBranchLogMismatch(MIPSOpcode op, u32 pc)
|
||||
{
|
||||
char temp[256];
|
||||
MIPSDisAsm(op, pc, temp, true);
|
||||
@ -106,13 +106,13 @@ static void JitBranchLogMismatch(u32 op, u32 pc)
|
||||
host->SetDebugMode(true);
|
||||
}
|
||||
|
||||
void Jit::BranchLog(u32 op)
|
||||
void Jit::BranchLog(MIPSOpcode op)
|
||||
{
|
||||
FlushAll();
|
||||
ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLog, 2), op, js.compilerPC);
|
||||
ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLog, 2), op.encoding, js.compilerPC);
|
||||
}
|
||||
|
||||
void Jit::BranchLogExit(u32 op, u32 dest, bool useEAX)
|
||||
void Jit::BranchLogExit(MIPSOpcode op, u32 dest, bool useEAX)
|
||||
{
|
||||
OpArg destArg = useEAX ? R(EAX) : Imm32(dest);
|
||||
|
||||
@ -120,7 +120,7 @@ void Jit::BranchLogExit(u32 op, u32 dest, bool useEAX)
|
||||
FixupBranch skip = J_CC(CC_E);
|
||||
|
||||
MOV(32, M((void *) &jitBranchExit), destArg);
|
||||
ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLogMismatch, 2), op, js.compilerPC);
|
||||
ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLogMismatch, 2), op.encoding, js.compilerPC);
|
||||
// Restore EAX, we probably ruined it.
|
||||
if (useEAX)
|
||||
MOV(32, R(EAX), M((void *) &jitBranchExit));
|
||||
@ -128,7 +128,7 @@ void Jit::BranchLogExit(u32 op, u32 dest, bool useEAX)
|
||||
SetJumpTarget(skip);
|
||||
}
|
||||
|
||||
void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely)
|
||||
void Jit::BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely)
|
||||
{
|
||||
CONDITIONAL_LOG;
|
||||
if (js.inDelaySlot) {
|
||||
@ -140,7 +140,7 @@ void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely)
|
||||
int rs = _RS;
|
||||
u32 targetAddr = js.compilerPC + offset + 4;
|
||||
|
||||
u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC+4);
|
||||
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC+4);
|
||||
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
|
||||
CONDITIONAL_NICE_DELAYSLOT;
|
||||
|
||||
@ -224,7 +224,7 @@ void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely)
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely)
|
||||
void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool likely)
|
||||
{
|
||||
CONDITIONAL_LOG;
|
||||
if (js.inDelaySlot) {
|
||||
@ -235,7 +235,7 @@ void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely)
|
||||
int rs = _RS;
|
||||
u32 targetAddr = js.compilerPC + offset + 4;
|
||||
|
||||
u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
|
||||
CONDITIONAL_NICE_DELAYSLOT;
|
||||
|
||||
@ -321,7 +321,7 @@ void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely)
|
||||
}
|
||||
|
||||
|
||||
void Jit::Comp_RelBranch(u32 op)
|
||||
void Jit::Comp_RelBranch(MIPSOpcode op)
|
||||
{
|
||||
switch (op>>26)
|
||||
{
|
||||
@ -343,7 +343,7 @@ void Jit::Comp_RelBranch(u32 op)
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_RelBranchRI(u32 op)
|
||||
void Jit::Comp_RelBranchRI(MIPSOpcode op)
|
||||
{
|
||||
switch ((op >> 16) & 0x1F)
|
||||
{
|
||||
@ -363,7 +363,7 @@ void Jit::Comp_RelBranchRI(u32 op)
|
||||
|
||||
|
||||
// If likely is set, discard the branch slot if NOT taken.
|
||||
void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely)
|
||||
void Jit::BranchFPFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)
|
||||
{
|
||||
CONDITIONAL_LOG;
|
||||
if (js.inDelaySlot) {
|
||||
@ -373,7 +373,7 @@ void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely)
|
||||
int offset = _IMM16 << 2;
|
||||
u32 targetAddr = js.compilerPC + offset + 4;
|
||||
|
||||
u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp);
|
||||
CONDITIONAL_NICE_DELAYSLOT;
|
||||
if (!likely && delaySlotIsNice)
|
||||
@ -419,7 +419,7 @@ void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely)
|
||||
}
|
||||
|
||||
|
||||
void Jit::Comp_FPUBranch(u32 op)
|
||||
void Jit::Comp_FPUBranch(MIPSOpcode op)
|
||||
{
|
||||
switch((op >> 16) & 0x1f)
|
||||
{
|
||||
@ -434,7 +434,7 @@ void Jit::Comp_FPUBranch(u32 op)
|
||||
}
|
||||
|
||||
// If likely is set, discard the branch slot if NOT taken.
|
||||
void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely)
|
||||
void Jit::BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)
|
||||
{
|
||||
CONDITIONAL_LOG;
|
||||
if (js.inDelaySlot) {
|
||||
@ -444,7 +444,7 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely)
|
||||
int offset = _IMM16 << 2;
|
||||
u32 targetAddr = js.compilerPC + offset + 4;
|
||||
|
||||
u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
|
||||
// Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)
|
||||
// The behavior is undefined - the CPU may take the second branch even if the first one passes.
|
||||
@ -503,7 +503,7 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely)
|
||||
}
|
||||
|
||||
|
||||
void Jit::Comp_VBranch(u32 op)
|
||||
void Jit::Comp_VBranch(MIPSOpcode op)
|
||||
{
|
||||
switch ((op >> 16) & 3)
|
||||
{
|
||||
@ -517,7 +517,7 @@ void Jit::Comp_VBranch(u32 op)
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_Jump(u32 op)
|
||||
void Jit::Comp_Jump(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_LOG;
|
||||
if (js.inDelaySlot) {
|
||||
@ -554,7 +554,7 @@ void Jit::Comp_Jump(u32 op)
|
||||
|
||||
static u32 savedPC;
|
||||
|
||||
void Jit::Comp_JumpReg(u32 op)
|
||||
void Jit::Comp_JumpReg(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_LOG;
|
||||
if (js.inDelaySlot) {
|
||||
@ -563,7 +563,7 @@ void Jit::Comp_JumpReg(u32 op)
|
||||
}
|
||||
int rs = _RS;
|
||||
|
||||
u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
|
||||
CONDITIONAL_NICE_DELAYSLOT;
|
||||
|
||||
@ -611,7 +611,7 @@ void Jit::Comp_JumpReg(u32 op)
|
||||
js.compiling = false;
|
||||
}
|
||||
|
||||
void Jit::Comp_Syscall(u32 op)
|
||||
void Jit::Comp_Syscall(MIPSOpcode op)
|
||||
{
|
||||
FlushAll();
|
||||
|
||||
@ -624,13 +624,13 @@ void Jit::Comp_Syscall(u32 op)
|
||||
if (op == GetSyscallOp("FakeSysCalls", NID_IDLE))
|
||||
ABI_CallFunction((void *)GetFunc("FakeSysCalls", NID_IDLE)->func);
|
||||
else
|
||||
ABI_CallFunctionC((void *)&CallSyscall, op);
|
||||
ABI_CallFunctionC((void *)&CallSyscall, op.encoding);
|
||||
|
||||
WriteSyscallExit();
|
||||
js.compiling = false;
|
||||
}
|
||||
|
||||
void Jit::Comp_Break(u32 op)
|
||||
void Jit::Comp_Break(MIPSOpcode op)
|
||||
{
|
||||
Comp_Generic(op);
|
||||
WriteSyscallExit();
|
||||
|
||||
@ -41,7 +41,7 @@
|
||||
namespace MIPSComp
|
||||
{
|
||||
|
||||
void Jit::CompFPTriArith(u32 op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters)
|
||||
void Jit::CompFPTriArith(MIPSOpcode op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters)
|
||||
{
|
||||
int ft = _FT;
|
||||
int fs = _FS;
|
||||
@ -72,7 +72,7 @@ void Jit::CompFPTriArith(u32 op, void (XEmitter::*arith)(X64Reg reg, OpArg), boo
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_FPU3op(u32 op)
|
||||
void Jit::Comp_FPU3op(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
switch (op & 0x3f)
|
||||
@ -89,7 +89,7 @@ void Jit::Comp_FPU3op(u32 op)
|
||||
|
||||
static u32 MEMORY_ALIGNED16(ssLoadStoreTemp);
|
||||
|
||||
void Jit::Comp_FPULS(u32 op)
|
||||
void Jit::Comp_FPULS(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
s32 offset = (s16)(op&0xFFFF);
|
||||
@ -171,7 +171,7 @@ void Jit::CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN)
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_FPUComp(u32 op)
|
||||
void Jit::Comp_FPUComp(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
@ -225,7 +225,7 @@ void Jit::Comp_FPUComp(u32 op)
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_FPU2op(u32 op) {
|
||||
void Jit::Comp_FPU2op(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
int fs = _FS;
|
||||
@ -290,7 +290,7 @@ void Jit::Comp_FPU2op(u32 op) {
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_mxc1(u32 op)
|
||||
void Jit::Comp_mxc1(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
|
||||
@ -41,7 +41,7 @@
|
||||
|
||||
namespace MIPSComp
|
||||
{
|
||||
void Jit::CompITypeMemRead(u32 op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc)
|
||||
void Jit::CompITypeMemRead(MIPSOpcode op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int offset = (signed short)(op&0xFFFF);
|
||||
@ -62,7 +62,7 @@ namespace MIPSComp
|
||||
gpr.UnlockAll();
|
||||
}
|
||||
|
||||
void Jit::CompITypeMemWrite(u32 op, u32 bits, void *safeFunc)
|
||||
void Jit::CompITypeMemWrite(MIPSOpcode op, u32 bits, void *safeFunc)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int offset = (signed short)(op&0xFFFF);
|
||||
@ -102,7 +102,7 @@ namespace MIPSComp
|
||||
gpr.UnlockAll();
|
||||
}
|
||||
|
||||
void Jit::CompITypeMemUnpairedLR(u32 op, bool isStore)
|
||||
void Jit::CompITypeMemUnpairedLR(MIPSOpcode op, bool isStore)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int o = op>>26;
|
||||
@ -159,7 +159,7 @@ namespace MIPSComp
|
||||
gpr.UnlockAllX();
|
||||
}
|
||||
|
||||
void Jit::CompITypeMemUnpairedLRInner(u32 op, X64Reg shiftReg)
|
||||
void Jit::CompITypeMemUnpairedLRInner(MIPSOpcode op, X64Reg shiftReg)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int o = op>>26;
|
||||
@ -251,7 +251,7 @@ namespace MIPSComp
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_ITypeMem(u32 op)
|
||||
void Jit::Comp_ITypeMem(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int offset = (signed short)(op&0xFFFF);
|
||||
@ -299,9 +299,9 @@ namespace MIPSComp
|
||||
|
||||
case 34: //lwl
|
||||
{
|
||||
u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
// Looking for lwr rd, offset-3(rs) which makes a pair.
|
||||
u32 desiredOp = ((op + (4 << 26)) & 0xFFFF0000) + (offset - 3);
|
||||
u32 desiredOp = ((op & 0xFFFF0000) + (4 << 26)) + (offset - 3);
|
||||
if (!js.inDelaySlot && nextOp == desiredOp)
|
||||
{
|
||||
EatInstruction(nextOp);
|
||||
@ -315,9 +315,9 @@ namespace MIPSComp
|
||||
|
||||
case 38: //lwr
|
||||
{
|
||||
u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
// Looking for lwl rd, offset+3(rs) which makes a pair.
|
||||
u32 desiredOp = ((op - (4 << 26)) & 0xFFFF0000) + (offset + 3);
|
||||
u32 desiredOp = ((op & 0xFFFF0000) - (4 << 26)) + (offset + 3);
|
||||
if (!js.inDelaySlot && nextOp == desiredOp)
|
||||
{
|
||||
EatInstruction(nextOp);
|
||||
@ -331,9 +331,9 @@ namespace MIPSComp
|
||||
|
||||
case 42: //swl
|
||||
{
|
||||
u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
// Looking for swr rd, offset-3(rs) which makes a pair.
|
||||
u32 desiredOp = ((op + (4 << 26)) & 0xFFFF0000) + (offset - 3);
|
||||
u32 desiredOp = ((op & 0xFFFF0000) + (4 << 26)) + (offset - 3);
|
||||
if (!js.inDelaySlot && nextOp == desiredOp)
|
||||
{
|
||||
EatInstruction(nextOp);
|
||||
@ -347,9 +347,9 @@ namespace MIPSComp
|
||||
|
||||
case 46: //swr
|
||||
{
|
||||
u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
|
||||
// Looking for swl rd, offset+3(rs) which makes a pair.
|
||||
u32 desiredOp = ((op - (4 << 26)) & 0xFFFF0000) + (offset + 3);
|
||||
u32 desiredOp = ((op & 0xFFFF0000) - (4 << 26)) + (offset + 3);
|
||||
if (!js.inDelaySlot && nextOp == desiredOp)
|
||||
{
|
||||
EatInstruction(nextOp);
|
||||
|
||||
@ -61,7 +61,7 @@ const u32 MEMORY_ALIGNED16( noSignMask[4] ) = {0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFF
|
||||
const u32 MEMORY_ALIGNED16( signBitLower[4] ) = {0x80000000, 0, 0, 0};
|
||||
const float MEMORY_ALIGNED16( oneOneOneOne[4] ) = {1.0f, 1.0f, 1.0f, 1.0f};
|
||||
|
||||
void Jit::Comp_VPFX(u32 op)
|
||||
void Jit::Comp_VPFX(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
int data = op & 0xFFFFF;
|
||||
@ -198,7 +198,7 @@ bool IsOverlapSafe(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[]
|
||||
|
||||
static u32 MEMORY_ALIGNED16(ssLoadStoreTemp);
|
||||
|
||||
void Jit::Comp_SV(u32 op) {
|
||||
void Jit::Comp_SV(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
s32 imm = (signed short)(op&0xFFFC);
|
||||
@ -262,7 +262,7 @@ void Jit::Comp_SV(u32 op) {
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_SVQ(u32 op)
|
||||
void Jit::Comp_SVQ(MIPSOpcode op)
|
||||
{
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
@ -412,7 +412,7 @@ void Jit::Comp_SVQ(u32 op)
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_VVectorInit(u32 op) {
|
||||
void Jit::Comp_VVectorInit(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -445,7 +445,7 @@ void Jit::Comp_VVectorInit(u32 op) {
|
||||
|
||||
|
||||
|
||||
void Jit::Comp_VIdt(u32 op) {
|
||||
void Jit::Comp_VIdt(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
int vd = _VD;
|
||||
@ -477,7 +477,7 @@ void Jit::Comp_VIdt(u32 op) {
|
||||
}
|
||||
|
||||
|
||||
void Jit::Comp_VDot(u32 op) {
|
||||
void Jit::Comp_VDot(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -521,7 +521,7 @@ void Jit::Comp_VDot(u32 op) {
|
||||
}
|
||||
|
||||
|
||||
void Jit::Comp_VHdp(u32 op) {
|
||||
void Jit::Comp_VHdp(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -568,7 +568,7 @@ void Jit::Comp_VHdp(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_VCrossQuat(u32 op) {
|
||||
void Jit::Comp_VCrossQuat(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -676,7 +676,7 @@ void Jit::Comp_VCrossQuat(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vcmov(u32 op) {
|
||||
void Jit::Comp_Vcmov(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -722,7 +722,7 @@ void Jit::Comp_Vcmov(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_VecDo3(u32 op) {
|
||||
void Jit::Comp_VecDo3(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -861,7 +861,7 @@ void Jit::Comp_VecDo3(u32 op) {
|
||||
|
||||
static float ssCompareTemp;
|
||||
|
||||
void Jit::Comp_Vcmp(u32 op) {
|
||||
void Jit::Comp_Vcmp(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -1009,11 +1009,11 @@ void Jit::Comp_Vcmp(u32 op) {
|
||||
gpr.UnlockAllX();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vsge(u32 op) {
|
||||
void Jit::Comp_Vsge(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_Vslt(u32 op) {
|
||||
void Jit::Comp_Vslt(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
@ -1030,7 +1030,7 @@ extern const float mulTableVi2f[32] = {
|
||||
1.0f/(1UL<<28),1.0f/(1UL<<29),1.0f/(1UL<<30),1.0f/(1UL<<31),
|
||||
};
|
||||
|
||||
void Jit::Comp_Vi2f(u32 op) {
|
||||
void Jit::Comp_Vi2f(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -1096,7 +1096,7 @@ static const float half = 0.5f;
|
||||
static double maxIntAsDouble = (double)0x7fffffff; // that's not equal to 0x80000000
|
||||
static double minIntAsDouble = (double)(int)0x80000000;
|
||||
|
||||
void Jit::Comp_Vf2i(u32 op) {
|
||||
void Jit::Comp_Vf2i(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
if (js.HasUnknownPrefix())
|
||||
DISABLE;
|
||||
@ -1165,7 +1165,7 @@ void Jit::Comp_Vf2i(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vcst(u32 op) {
|
||||
void Jit::Comp_Vcst(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -1189,7 +1189,7 @@ void Jit::Comp_Vcst(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_VV2Op(u32 op) {
|
||||
void Jit::Comp_VV2Op(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -1313,7 +1313,7 @@ void Jit::Comp_VV2Op(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_Mftv(u32 op) {
|
||||
void Jit::Comp_Mftv(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
int imm = op & 0xFF;
|
||||
@ -1368,7 +1368,7 @@ void Jit::Comp_Mftv(u32 op) {
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_Vmtvc(u32 op) {
|
||||
void Jit::Comp_Vmtvc(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
int vs = _VS;
|
||||
int imm = op & 0xFF;
|
||||
@ -1387,7 +1387,7 @@ void Jit::Comp_Vmtvc(u32 op) {
|
||||
}
|
||||
}
|
||||
|
||||
void Jit::Comp_VMatrixInit(u32 op) {
|
||||
void Jit::Comp_VMatrixInit(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -1430,7 +1430,7 @@ void Jit::Comp_VMatrixInit(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vmmov(u32 op) {
|
||||
void Jit::Comp_Vmmov(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
// TODO: This probably ignores prefixes?
|
||||
@ -1472,7 +1472,7 @@ void Jit::Comp_Vmmov(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_VScl(u32 op) {
|
||||
void Jit::Comp_VScl(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -1523,7 +1523,7 @@ void Jit::Comp_VScl(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vmmul(u32 op) {
|
||||
void Jit::Comp_Vmmul(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
// TODO: This probably ignores prefixes?
|
||||
@ -1587,7 +1587,7 @@ void Jit::Comp_Vmmul(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vmscl(u32 op) {
|
||||
void Jit::Comp_Vmscl(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
// TODO: This probably ignores prefixes?
|
||||
@ -1632,7 +1632,7 @@ void Jit::Comp_Vmscl(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vtfm(u32 op) {
|
||||
void Jit::Comp_Vtfm(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
// TODO: This probably ignores prefixes? Or maybe uses D?
|
||||
@ -1689,27 +1689,27 @@ void Jit::Comp_Vtfm(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_VCrs(u32 op) {
|
||||
void Jit::Comp_VCrs(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_VDet(u32 op) {
|
||||
void Jit::Comp_VDet(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_Vi2x(u32 op) {
|
||||
void Jit::Comp_Vi2x(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_Vx2i(u32 op) {
|
||||
void Jit::Comp_Vx2i(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_Vhoriz(u32 op) {
|
||||
void Jit::Comp_Vhoriz(MIPSOpcode op) {
|
||||
DISABLE;
|
||||
}
|
||||
|
||||
void Jit::Comp_Viim(u32 op) {
|
||||
void Jit::Comp_Viim(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -1729,7 +1729,7 @@ void Jit::Comp_Viim(u32 op) {
|
||||
fpr.ReleaseSpillLocks();
|
||||
}
|
||||
|
||||
void Jit::Comp_Vfim(u32 op) {
|
||||
void Jit::Comp_Vfim(MIPSOpcode op) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
if (js.HasUnknownPrefix())
|
||||
@ -1769,7 +1769,7 @@ void SinCosNegSin(float angle) {
|
||||
sincostemp[1] = cosf(angle);
|
||||
}
|
||||
// Very heavily used by FF:CC
|
||||
void Jit::Comp_VRot(u32 op) {
|
||||
void Jit::Comp_VRot(MIPSOpcode op) {
|
||||
// DISABLE;
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
|
||||
@ -97,7 +97,7 @@ u32 JitBreakpoint()
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void JitLogMiss(u32 op)
|
||||
static void JitLogMiss(MIPSOpcode op)
|
||||
{
|
||||
if (USE_JIT_MISSMAP)
|
||||
notJitOps[MIPSGetName(op)]++;
|
||||
@ -205,7 +205,7 @@ void Jit::CompileDelaySlot(int flags, RegCacheState *state)
|
||||
SAVE_FLAGS; // preserve flag around the delay slot!
|
||||
|
||||
js.inDelaySlot = true;
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
MIPSCompileOp(op);
|
||||
js.inDelaySlot = false;
|
||||
|
||||
@ -223,13 +223,13 @@ void Jit::CompileDelaySlot(int flags, RegCacheState *state)
|
||||
void Jit::CompileAt(u32 addr)
|
||||
{
|
||||
CheckJitBreakpoint(addr, 0);
|
||||
u32 op = Memory::Read_Instruction(addr);
|
||||
MIPSOpcode op = Memory::Read_Instruction(addr);
|
||||
MIPSCompileOp(op);
|
||||
}
|
||||
|
||||
void Jit::EatInstruction(u32 op)
|
||||
void Jit::EatInstruction(MIPSOpcode op)
|
||||
{
|
||||
u32 info = MIPSGetInfo(op);
|
||||
MIPSInfo info = MIPSGetInfo(op);
|
||||
_dbg_assert_msg_(JIT, !(info & DELAYSLOT), "Never eat a branch op.");
|
||||
_dbg_assert_msg_(JIT, !js.inDelaySlot, "Never eat an instruction inside a delayslot.");
|
||||
|
||||
@ -292,8 +292,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
|
||||
|
||||
b->normalEntry = GetCodePtr();
|
||||
|
||||
// TODO: this needs work
|
||||
MIPSAnalyst::AnalysisResults analysis; // = MIPSAnalyst::Analyze(em_address);
|
||||
MIPSAnalyst::AnalysisResults analysis = MIPSAnalyst::Analyze(em_address);
|
||||
|
||||
gpr.Start(mips_, analysis);
|
||||
fpr.Start(mips_, analysis);
|
||||
@ -303,7 +302,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
|
||||
// Jit breakpoints are quite fast, so let's do them in release too.
|
||||
CheckJitBreakpoint(js.compilerPC, 0);
|
||||
|
||||
u32 inst = Memory::Read_Instruction(js.compilerPC);
|
||||
MIPSOpcode inst = Memory::Read_Instruction(js.compilerPC);
|
||||
js.downcountAmount += MIPSGetInstructionCycleEstimate(inst);
|
||||
|
||||
MIPSCompileOp(inst);
|
||||
@ -338,13 +337,13 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
|
||||
return b->normalEntry;
|
||||
}
|
||||
|
||||
void Jit::Comp_RunBlock(u32 op)
|
||||
void Jit::Comp_RunBlock(MIPSOpcode op)
|
||||
{
|
||||
// This shouldn't be necessary, the dispatcher should catch us before we get here.
|
||||
ERROR_LOG(DYNA_REC, "Comp_RunBlock");
|
||||
}
|
||||
|
||||
void Jit::Comp_Generic(u32 op)
|
||||
void Jit::Comp_Generic(MIPSOpcode op)
|
||||
{
|
||||
FlushAll();
|
||||
MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
|
||||
@ -354,14 +353,14 @@ void Jit::Comp_Generic(u32 op)
|
||||
{
|
||||
MOV(32, M(&mips_->pc), Imm32(js.compilerPC));
|
||||
if (USE_JIT_MISSMAP)
|
||||
ABI_CallFunctionC((void *)&JitLogMiss, op);
|
||||
ABI_CallFunctionC((void *)&JitLogMiss, op.encoding);
|
||||
else
|
||||
ABI_CallFunctionC((void *)func, op);
|
||||
ABI_CallFunctionC((void *)func, op.encoding);
|
||||
}
|
||||
else
|
||||
ERROR_LOG_REPORT(JIT, "Trying to compile instruction that can't be interpreted");
|
||||
|
||||
const int info = MIPSGetInfo(op);
|
||||
const MIPSInfo info = MIPSGetInfo(op);
|
||||
if ((info & IS_VFPU) != 0 && (info & VFPU_NO_PREFIX) == 0)
|
||||
{
|
||||
// If it does eat them, it'll happen in MIPSCompileOp().
|
||||
@ -868,6 +867,6 @@ void Jit::CallProtectedFunction(void *func, const OpArg &arg1, const u32 arg2, c
|
||||
ABI_CallFunction((void *)thunks.GetLoadRegsFunction());
|
||||
}
|
||||
|
||||
void Jit::Comp_DoNothing(u32 op) { }
|
||||
void Jit::Comp_DoNothing(MIPSOpcode op) { }
|
||||
|
||||
} // namespace
|
||||
|
||||
@ -176,7 +176,7 @@ public:
|
||||
// Compiled ops should ignore delay slots
|
||||
// the compiler will take care of them by itself
|
||||
// OR NOT
|
||||
void Comp_Generic(u32 op);
|
||||
void Comp_Generic(MIPSOpcode op);
|
||||
|
||||
void RunLoopUntil(u64 globalticks);
|
||||
|
||||
@ -184,70 +184,70 @@ public:
|
||||
const u8 *DoJit(u32 em_address, JitBlock *b);
|
||||
|
||||
void CompileAt(u32 addr);
|
||||
void Comp_RunBlock(u32 op);
|
||||
void Comp_RunBlock(MIPSOpcode op);
|
||||
|
||||
// Ops
|
||||
void Comp_ITypeMem(u32 op);
|
||||
void Comp_ITypeMem(MIPSOpcode op);
|
||||
|
||||
void Comp_RelBranch(u32 op);
|
||||
void Comp_RelBranchRI(u32 op);
|
||||
void Comp_FPUBranch(u32 op);
|
||||
void Comp_FPULS(u32 op);
|
||||
void Comp_FPUComp(u32 op);
|
||||
void Comp_Jump(u32 op);
|
||||
void Comp_JumpReg(u32 op);
|
||||
void Comp_Syscall(u32 op);
|
||||
void Comp_Break(u32 op);
|
||||
void Comp_RelBranch(MIPSOpcode op);
|
||||
void Comp_RelBranchRI(MIPSOpcode op);
|
||||
void Comp_FPUBranch(MIPSOpcode op);
|
||||
void Comp_FPULS(MIPSOpcode op);
|
||||
void Comp_FPUComp(MIPSOpcode op);
|
||||
void Comp_Jump(MIPSOpcode op);
|
||||
void Comp_JumpReg(MIPSOpcode op);
|
||||
void Comp_Syscall(MIPSOpcode op);
|
||||
void Comp_Break(MIPSOpcode op);
|
||||
|
||||
void Comp_IType(u32 op);
|
||||
void Comp_RType2(u32 op);
|
||||
void Comp_RType3(u32 op);
|
||||
void Comp_ShiftType(u32 op);
|
||||
void Comp_Allegrex(u32 op);
|
||||
void Comp_Allegrex2(u32 op);
|
||||
void Comp_VBranch(u32 op);
|
||||
void Comp_MulDivType(u32 op);
|
||||
void Comp_Special3(u32 op);
|
||||
void Comp_IType(MIPSOpcode op);
|
||||
void Comp_RType2(MIPSOpcode op);
|
||||
void Comp_RType3(MIPSOpcode op);
|
||||
void Comp_ShiftType(MIPSOpcode op);
|
||||
void Comp_Allegrex(MIPSOpcode op);
|
||||
void Comp_Allegrex2(MIPSOpcode op);
|
||||
void Comp_VBranch(MIPSOpcode op);
|
||||
void Comp_MulDivType(MIPSOpcode op);
|
||||
void Comp_Special3(MIPSOpcode op);
|
||||
|
||||
void Comp_FPU3op(u32 op);
|
||||
void Comp_FPU2op(u32 op);
|
||||
void Comp_mxc1(u32 op);
|
||||
void Comp_FPU3op(MIPSOpcode op);
|
||||
void Comp_FPU2op(MIPSOpcode op);
|
||||
void Comp_mxc1(MIPSOpcode op);
|
||||
|
||||
void Comp_SV(u32 op);
|
||||
void Comp_SVQ(u32 op);
|
||||
void Comp_VPFX(u32 op);
|
||||
void Comp_VVectorInit(u32 op);
|
||||
void Comp_VMatrixInit(u32 op);
|
||||
void Comp_VDot(u32 op);
|
||||
void Comp_VecDo3(u32 op);
|
||||
void Comp_VV2Op(u32 op);
|
||||
void Comp_Mftv(u32 op);
|
||||
void Comp_Vmtvc(u32 op);
|
||||
void Comp_Vmmov(u32 op);
|
||||
void Comp_VScl(u32 op);
|
||||
void Comp_Vmmul(u32 op);
|
||||
void Comp_Vmscl(u32 op);
|
||||
void Comp_Vtfm(u32 op);
|
||||
void Comp_VHdp(u32 op);
|
||||
void Comp_VCrs(u32 op);
|
||||
void Comp_VDet(u32 op);
|
||||
void Comp_Vi2x(u32 op);
|
||||
void Comp_Vx2i(u32 op);
|
||||
void Comp_Vf2i(u32 op);
|
||||
void Comp_Vi2f(u32 op);
|
||||
void Comp_Vcst(u32 op);
|
||||
void Comp_Vhoriz(u32 op);
|
||||
void Comp_VRot(u32 op);
|
||||
void Comp_VIdt(u32 op);
|
||||
void Comp_Vcmp(u32 op);
|
||||
void Comp_Vcmov(u32 op);
|
||||
void Comp_Viim(u32 op);
|
||||
void Comp_Vfim(u32 op);
|
||||
void Comp_VCrossQuat(u32 op);
|
||||
void Comp_Vsge(u32 op);
|
||||
void Comp_Vslt(u32 op);
|
||||
void Comp_SV(MIPSOpcode op);
|
||||
void Comp_SVQ(MIPSOpcode op);
|
||||
void Comp_VPFX(MIPSOpcode op);
|
||||
void Comp_VVectorInit(MIPSOpcode op);
|
||||
void Comp_VMatrixInit(MIPSOpcode op);
|
||||
void Comp_VDot(MIPSOpcode op);
|
||||
void Comp_VecDo3(MIPSOpcode op);
|
||||
void Comp_VV2Op(MIPSOpcode op);
|
||||
void Comp_Mftv(MIPSOpcode op);
|
||||
void Comp_Vmtvc(MIPSOpcode op);
|
||||
void Comp_Vmmov(MIPSOpcode op);
|
||||
void Comp_VScl(MIPSOpcode op);
|
||||
void Comp_Vmmul(MIPSOpcode op);
|
||||
void Comp_Vmscl(MIPSOpcode op);
|
||||
void Comp_Vtfm(MIPSOpcode op);
|
||||
void Comp_VHdp(MIPSOpcode op);
|
||||
void Comp_VCrs(MIPSOpcode op);
|
||||
void Comp_VDet(MIPSOpcode op);
|
||||
void Comp_Vi2x(MIPSOpcode op);
|
||||
void Comp_Vx2i(MIPSOpcode op);
|
||||
void Comp_Vf2i(MIPSOpcode op);
|
||||
void Comp_Vi2f(MIPSOpcode op);
|
||||
void Comp_Vcst(MIPSOpcode op);
|
||||
void Comp_Vhoriz(MIPSOpcode op);
|
||||
void Comp_VRot(MIPSOpcode op);
|
||||
void Comp_VIdt(MIPSOpcode op);
|
||||
void Comp_Vcmp(MIPSOpcode op);
|
||||
void Comp_Vcmov(MIPSOpcode op);
|
||||
void Comp_Viim(MIPSOpcode op);
|
||||
void Comp_Vfim(MIPSOpcode op);
|
||||
void Comp_VCrossQuat(MIPSOpcode op);
|
||||
void Comp_Vsge(MIPSOpcode op);
|
||||
void Comp_Vslt(MIPSOpcode op);
|
||||
|
||||
void Comp_DoNothing(u32 op);
|
||||
void Comp_DoNothing(MIPSOpcode op);
|
||||
|
||||
void ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz);
|
||||
void ApplyPrefixD(const u8 *vregs, VectorSize sz);
|
||||
@ -281,7 +281,7 @@ private:
|
||||
void CompileDelaySlot(int flags, RegCacheState &state) {
|
||||
CompileDelaySlot(flags, &state);
|
||||
}
|
||||
void EatInstruction(u32 op);
|
||||
void EatInstruction(MIPSOpcode op);
|
||||
|
||||
void WriteExit(u32 destination, int exit_num);
|
||||
void WriteExitDestInEAX();
|
||||
@ -290,24 +290,24 @@ private:
|
||||
bool CheckJitBreakpoint(u32 addr, int downcountOffset);
|
||||
|
||||
// Utility compilation functions
|
||||
void BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely);
|
||||
void BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely);
|
||||
void BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely);
|
||||
void BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely);
|
||||
void BranchLog(u32 op);
|
||||
void BranchLogExit(u32 op, u32 dest, bool useEAX);
|
||||
void BranchFPFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely);
|
||||
void BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely);
|
||||
void BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool likely);
|
||||
void BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely);
|
||||
void BranchLog(MIPSOpcode op);
|
||||
void BranchLogExit(MIPSOpcode op, u32 dest, bool useEAX);
|
||||
|
||||
// Utilities to reduce duplicated code
|
||||
void CompImmLogic(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &));
|
||||
void CompTriArith(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &), u32 (*doImm)(const u32, const u32));
|
||||
void CompShiftImm(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32));
|
||||
void CompShiftVar(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32));
|
||||
void CompITypeMemRead(u32 op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc);
|
||||
void CompITypeMemWrite(u32 op, u32 bits, void *safeFunc);
|
||||
void CompITypeMemUnpairedLR(u32 op, bool isStore);
|
||||
void CompITypeMemUnpairedLRInner(u32 op, X64Reg shiftReg);
|
||||
void CompImmLogic(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &));
|
||||
void CompTriArith(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &), u32 (*doImm)(const u32, const u32));
|
||||
void CompShiftImm(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32));
|
||||
void CompShiftVar(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32));
|
||||
void CompITypeMemRead(MIPSOpcode op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc);
|
||||
void CompITypeMemWrite(MIPSOpcode op, u32 bits, void *safeFunc);
|
||||
void CompITypeMemUnpairedLR(MIPSOpcode op, bool isStore);
|
||||
void CompITypeMemUnpairedLRInner(MIPSOpcode op, X64Reg shiftReg);
|
||||
|
||||
void CompFPTriArith(u32 op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters);
|
||||
void CompFPTriArith(MIPSOpcode op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters);
|
||||
void CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN = false);
|
||||
|
||||
void CallProtectedFunction(void *func, const OpArg &arg1);
|
||||
@ -395,7 +395,7 @@ private:
|
||||
friend class JitSafeMem;
|
||||
};
|
||||
|
||||
typedef void (Jit::*MIPSCompileFunc)(u32 opcode);
|
||||
typedef void (Jit::*MIPSCompileFunc)(MIPSOpcode opcode);
|
||||
|
||||
} // namespace MIPSComp
|
||||
|
||||
|
||||
@ -17,8 +17,8 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "x64Emitter.h"
|
||||
#include "../MIPSAnalyst.h"
|
||||
#include "Common/x64Emitter.h"
|
||||
#include "Core/MIPS/MIPSAnalyst.h"
|
||||
|
||||
using namespace Gen;
|
||||
|
||||
|
||||
@ -122,9 +122,9 @@ void Clear()
|
||||
memset(m_pVRAM, 0, VRAM_SIZE);
|
||||
}
|
||||
|
||||
u32 Read_Instruction(u32 address)
|
||||
Opcode Read_Instruction(u32 address)
|
||||
{
|
||||
u32 inst = Read_U32(address);
|
||||
Opcode inst = Opcode(Read_U32(address));
|
||||
if (MIPS_IS_EMUHACK(inst) && MIPSComp::jit)
|
||||
{
|
||||
JitBlockCache *bc = MIPSComp::jit->GetBlockCache();
|
||||
@ -139,16 +139,16 @@ u32 Read_Instruction(u32 address)
|
||||
}
|
||||
}
|
||||
|
||||
u32 Read_Opcode_JIT(u32 address)
|
||||
Opcode Read_Opcode_JIT(u32 address)
|
||||
{
|
||||
return Read_Instruction(address);
|
||||
}
|
||||
|
||||
// WARNING! No checks!
|
||||
// We assume that _Address is cached
|
||||
void Write_Opcode_JIT(const u32 _Address, const u32 _Value)
|
||||
void Write_Opcode_JIT(const u32 _Address, const Opcode _Value)
|
||||
{
|
||||
Memory::WriteUnchecked_U32(_Value, _Address);
|
||||
Memory::WriteUnchecked_U32(_Value.encoding, _Address);
|
||||
}
|
||||
|
||||
void Memset(const u32 _Address, const u8 _iValue, const u32 _iLength)
|
||||
|
||||
@ -97,13 +97,40 @@ void Shutdown();
|
||||
void DoState(PointerWrap &p);
|
||||
void Clear();
|
||||
|
||||
struct Opcode {
|
||||
Opcode() {
|
||||
encoding = 0;
|
||||
}
|
||||
|
||||
explicit Opcode(u32 v) : encoding (v) {
|
||||
}
|
||||
|
||||
u32 operator & (const u32 &arg) const {
|
||||
return encoding & arg;
|
||||
}
|
||||
|
||||
u32 operator >> (const u32 &arg) const {
|
||||
return encoding >> arg;
|
||||
}
|
||||
|
||||
bool operator == (const u32 &arg) const {
|
||||
return encoding == arg;
|
||||
}
|
||||
|
||||
bool operator != (const u32 &arg) const {
|
||||
return encoding != arg;
|
||||
}
|
||||
|
||||
u32 encoding;
|
||||
};
|
||||
|
||||
// used by JIT to read instructions
|
||||
u32 Read_Opcode_JIT(const u32 _Address);
|
||||
Opcode Read_Opcode_JIT(const u32 _Address);
|
||||
// used by JIT. uses iCacheJIT. Reads in the "Locked cache" mode
|
||||
void Write_Opcode_JIT(const u32 _Address, const u32 _Value);
|
||||
void Write_Opcode_JIT(const u32 _Address, const Opcode _Value);
|
||||
// this is used by Debugger a lot.
|
||||
// For now, just reads from memory!
|
||||
u32 Read_Instruction(const u32 _Address);
|
||||
Opcode Read_Instruction(const u32 _Address);
|
||||
|
||||
|
||||
// For use by emulator
|
||||
|
||||
Loading…
Reference in New Issue
Block a user