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jit-ir: Add load/store reorder and merge passes.
Can do more in merge, potentially. Maybe it's not useful...
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commit
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@ -236,6 +236,8 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, std::v
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&OptimizeFPMoves,
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&PropagateConstants,
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&PurgeTemps,
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// &ReorderLoadStore,
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// &MergeLoadStore,
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// &ThreeOpToTwoOp,
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};
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if (IRApplyPasses(passes, ARRAY_SIZE(passes), ir, simplified))
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@ -1,4 +1,5 @@
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#include <utility>
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#include <algorithm>
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#include "Common/Log.h"
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#include "Core/MIPS/IR/IRInterpreter.h"
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@ -744,3 +745,364 @@ bool ReduceLoads(const IRWriter &in, IRWriter &out) {
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return logBlocks;
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}
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static std::vector<IRInst> ReorderLoadStoreOps(std::vector<IRInst> &ops, const u32 *consts) {
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if (ops.size() < 2) {
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return ops;
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}
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bool modifiedRegs[256] = {};
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for (size_t i = 0, n = ops.size(); i < n - 1; ++i) {
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bool modifiesReg = false;
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bool usesFloatReg = false;
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switch (ops[i].op) {
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case IROp::Load8:
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case IROp::Load8Ext:
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case IROp::Load16:
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case IROp::Load16Ext:
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case IROp::Load32:
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modifiesReg = true;
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if (ops[i].src1 == ops[i].dest) {
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// Can't ever reorder these, since it changes.
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continue;
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}
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break;
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case IROp::Store8:
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case IROp::Store16:
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case IROp::Store32:
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break;
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case IROp::LoadFloat:
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case IROp::LoadVec4:
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usesFloatReg = true;
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modifiesReg = true;
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break;
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case IROp::StoreFloat:
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case IROp::StoreVec4:
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usesFloatReg = true;
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break;
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default:
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continue;
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}
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memset(modifiedRegs, 0, sizeof(modifiedRegs));
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size_t start = i;
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size_t j;
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for (j = i; j < n; ++j) {
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if (ops[start].op != ops[j].op || ops[start].src1 != ops[j].src1) {
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// Incompatible ops, so let's not reorder.
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break;
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}
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if (modifiedRegs[ops[j].dest] || (!usesFloatReg && modifiedRegs[ops[j].src1])) {
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// Can't reorder, this reg was modified.
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break;
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}
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if (modifiesReg) {
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// Modifies itself, can't reorder this.
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if (!usesFloatReg && ops[j].dest == ops[j].src1) {
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break;
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}
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modifiedRegs[ops[j].dest] = true;
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}
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// Keep going, these operations are compatible.
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}
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// Everything up to (but not including) j will be sorted, so skip them.
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i = j - 1;
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size_t end = j;
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if (start + 1 < end) {
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std::stable_sort(ops.begin() + start, ops.begin() + end, [&](const IRInst &a, const IRInst &b) {
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return consts[a.src2] < consts[b.src2];
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});
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}
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}
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return ops;
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}
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bool ReorderLoadStore(const IRWriter &in, IRWriter &out) {
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bool logBlocks = false;
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enum class RegState : u8 {
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UNUSED = 0,
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READ = 1,
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CHANGED = 2,
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};
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bool queuing = false;
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std::vector<IRInst> loadStoreQueue;
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std::vector<IRInst> otherQueue;
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RegState otherRegs[256] = {};
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auto flushQueue = [&]() {
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if (!queuing) {
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return;
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}
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std::vector<IRInst> loadStoreUnsorted = loadStoreQueue;
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std::vector<IRInst> loadStoreSorted = ReorderLoadStoreOps(loadStoreQueue, &in.GetConstants()[0]);
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if (memcmp(&loadStoreSorted[0], &loadStoreUnsorted[0], sizeof(IRInst) * loadStoreSorted.size()) != 0) {
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logBlocks = true;
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}
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queuing = false;
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for (IRInst queued : loadStoreSorted) {
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out.Write(queued);
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}
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for (IRInst queued : otherQueue) {
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out.Write(queued);
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}
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loadStoreQueue.clear();
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otherQueue.clear();
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memset(otherRegs, 0, sizeof(otherRegs));
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};
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for (int i = 0; i < (int)in.GetInstructions().size(); i++) {
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IRInst inst = in.GetInstructions()[i];
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switch (inst.op) {
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case IROp::Load8:
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case IROp::Load8Ext:
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case IROp::Load16:
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case IROp::Load16Ext:
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case IROp::Load32:
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// To move a load up, its dest can't be changed by things we move down.
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if (otherRegs[inst.dest] != RegState::UNUSED || otherRegs[inst.src1] == RegState::CHANGED) {
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flushQueue();
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}
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queuing = true;
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loadStoreQueue.push_back(inst);
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break;
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case IROp::Store8:
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case IROp::Store16:
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case IROp::Store32:
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// A store can move above even if it's read, as long as it's not changed by the other ops.
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if (otherRegs[inst.src3] == RegState::CHANGED || otherRegs[inst.src1] == RegState::CHANGED) {
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flushQueue();
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}
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queuing = true;
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loadStoreQueue.push_back(inst);
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break;
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case IROp::LoadVec4:
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case IROp::LoadFloat:
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case IROp::StoreVec4:
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case IROp::StoreFloat:
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// Floats can always move as long as their address is safe.
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if (otherRegs[inst.src1] == RegState::CHANGED) {
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flushQueue();
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}
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queuing = true;
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loadStoreQueue.push_back(inst);
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break;
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case IROp::Sub:
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case IROp::Slt:
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case IROp::SltU:
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case IROp::Add:
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case IROp::And:
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case IROp::Or:
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case IROp::Xor:
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case IROp::Shl:
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case IROp::Shr:
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case IROp::Ror:
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case IROp::Sar:
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case IROp::MovZ:
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case IROp::MovNZ:
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case IROp::Max:
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case IROp::Min:
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// We'll try to move this downward.
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otherRegs[inst.dest] = RegState::CHANGED;
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if (inst.src1 && otherRegs[inst.src1] != RegState::CHANGED)
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otherRegs[inst.src1] = RegState::READ;
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if (inst.src2 && otherRegs[inst.src2] != RegState::CHANGED)
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otherRegs[inst.src2] = RegState::READ;
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otherQueue.push_back(inst);
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queuing = true;
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break;
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case IROp::Neg:
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case IROp::Not:
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case IROp::BSwap16:
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case IROp::BSwap32:
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case IROp::Ext8to32:
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case IROp::Ext16to32:
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case IROp::ReverseBits:
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case IROp::Clz:
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case IROp::AddConst:
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case IROp::SubConst:
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case IROp::AndConst:
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case IROp::OrConst:
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case IROp::XorConst:
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case IROp::SltConst:
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case IROp::SltUConst:
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case IROp::ShlImm:
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case IROp::ShrImm:
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case IROp::RorImm:
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case IROp::SarImm:
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case IROp::Mov:
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// We'll try to move this downward.
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otherRegs[inst.dest] = RegState::CHANGED;
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if (inst.src1 && otherRegs[inst.src1] != RegState::CHANGED)
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otherRegs[inst.src1] = RegState::READ;
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otherQueue.push_back(inst);
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queuing = true;
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break;
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case IROp::SetConst:
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// We'll try to move this downward.
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otherRegs[inst.dest] = RegState::CHANGED;
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otherQueue.push_back(inst);
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queuing = true;
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break;
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case IROp::Mult:
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case IROp::MultU:
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case IROp::Madd:
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case IROp::MaddU:
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case IROp::Msub:
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case IROp::MsubU:
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case IROp::Div:
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case IROp::DivU:
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if (inst.src1 && otherRegs[inst.src1] != RegState::CHANGED)
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otherRegs[inst.src1] = RegState::READ;
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if (inst.src2 && otherRegs[inst.src2] != RegState::CHANGED)
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otherRegs[inst.src2] = RegState::READ;
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otherQueue.push_back(inst);
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queuing = true;
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break;
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case IROp::MfHi:
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case IROp::MfLo:
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case IROp::FpCondToReg:
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otherRegs[inst.dest] = RegState::CHANGED;
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otherQueue.push_back(inst);
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queuing = true;
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break;
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case IROp::MtHi:
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case IROp::MtLo:
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if (inst.src1 && otherRegs[inst.src1] != RegState::CHANGED)
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otherRegs[inst.src1] = RegState::READ;
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otherQueue.push_back(inst);
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queuing = true;
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break;
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case IROp::Nop:
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case IROp::Downcount:
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case IROp::ZeroFpCond:
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if (queuing) {
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// These are freebies. Sometimes helps with delay slots.
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otherQueue.push_back(inst);
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} else {
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out.Write(inst);
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}
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break;
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default:
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flushQueue();
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out.Write(inst);
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break;
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}
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}
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// Can reuse the old constants array - not touching constants in this pass.
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for (u32 value : in.GetConstants()) {
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out.AddConstant(value);
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}
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return logBlocks;
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}
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bool MergeLoadStore(const IRWriter &in, IRWriter &out) {
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bool logBlocks = false;
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auto opsCompatible = [&](const IRInst &a, const IRInst &b, int dist) {
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if (a.op != b.op || a.src1 != b.src1) {
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// Not similar enough at all.
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return false;
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}
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u32 off1 = in.GetConstants()[a.src2];
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u32 off2 = in.GetConstants()[b.src2];
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if (off1 + dist != off2) {
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// Not immediately sequential.
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return false;
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}
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return true;
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};
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for (int i = 0, n = (int)in.GetInstructions().size(); i < n; i++) {
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IRInst inst = in.GetInstructions()[i];
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int c = 0;
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switch (inst.op) {
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case IROp::Store8:
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for (c = 1; c < 4 && i + c < n; ++c) {
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const IRInst &nextInst = in.GetInstructions()[i + c];
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// TODO: Might be nice to check if this is an obvious constant.
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if (inst.src3 != nextInst.src3 || inst.src3 != 0) {
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break;
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}
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if (!opsCompatible(inst, nextInst, c)) {
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break;
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}
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}
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// Warning: this may generate unaligned stores.
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if (c == 2 || c == 3) {
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inst.op = IROp::Store16;
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out.Write(inst);
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// Skip the next one.
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++i;
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continue;
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}
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if (c == 4) {
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inst.op = IROp::Store32;
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out.Write(inst);
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// Skip all 4.
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i += 3;
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continue;
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}
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out.Write(inst);
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break;
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case IROp::Store16:
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for (c = 1; c < 2 && i + c < n; ++c) {
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const IRInst &nextInst = in.GetInstructions()[i + c];
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// TODO: Might be nice to check if this is an obvious constant.
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if (inst.src3 != nextInst.src3 || inst.src3 != 0) {
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break;
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}
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if (!opsCompatible(inst, nextInst, c * 2)) {
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break;
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}
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}
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// Warning: this may generate unaligned stores.
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if (c == 2) {
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inst.op = IROp::Store32;
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out.Write(inst);
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// Skip the next one.
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++i;
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continue;
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}
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out.Write(inst);
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break;
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default:
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out.Write(inst);
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break;
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}
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}
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// Can reuse the old constants array - not touching constants in this pass.
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for (u32 value : in.GetConstants()) {
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out.AddConstant(value);
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}
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return logBlocks;
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}
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@ -11,3 +11,5 @@ bool PurgeTemps(const IRWriter &in, IRWriter &out);
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bool ReduceLoads(const IRWriter &in, IRWriter &out);
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bool ThreeOpToTwoOp(const IRWriter &in, IRWriter &out);
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bool OptimizeFPMoves(const IRWriter &in, IRWriter &out);
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bool ReorderLoadStore(const IRWriter &in, IRWriter &out);
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bool MergeLoadStore(const IRWriter &in, IRWriter &out);
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