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A branch was missing inDelaySlot, refactor it.
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@ -154,7 +154,6 @@ void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely)
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}
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FlushAll();
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js.inDelaySlot = true;
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Gen::FixupBranch ptr;
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if (!likely)
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{
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@ -166,7 +165,6 @@ void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely)
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ptr = J_CC(cc, true);
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CompileDelaySlot(false);
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}
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js.inDelaySlot = false;
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// Take the branch
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CONDITIONAL_LOG_EXIT(targetAddr);
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@ -205,7 +203,6 @@ void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool likely)
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FlushAll();
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Gen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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CompileDelaySlot(!delaySlotIsNice);
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@ -216,7 +213,6 @@ void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool likely)
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ptr = J_CC(cc, true);
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CompileDelaySlot(false);
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}
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js.inDelaySlot = false;
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// Take the branch
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CONDITIONAL_LOG_EXIT(targetAddr);
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@ -295,7 +291,6 @@ void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely)
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TEST(32, M((void *)&(mips_->fpcond)), Imm32(1));
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Gen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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CompileDelaySlot(!delaySlotIsNice);
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@ -306,7 +301,6 @@ void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely)
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ptr = J_CC(cc, true);
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CompileDelaySlot(false);
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}
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js.inDelaySlot = false;
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// Take the branch
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CONDITIONAL_LOG_EXIT(targetAddr);
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@ -365,7 +359,6 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely)
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//int val = (mips_->vfpuCtrl[VFPU_CTRL_CC] >> imm3) & 1;
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TEST(32, M((void *)&(mips_->vfpuCtrl[VFPU_CTRL_CC])), Imm32(1 << imm3));
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Gen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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CompileDelaySlot(!delaySlotIsNice);
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@ -376,7 +369,6 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely)
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ptr = J_CC(cc, true);
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CompileDelaySlot(false);
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}
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js.inDelaySlot = false;
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// Take the branch
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CONDITIONAL_LOG_EXIT(targetAddr);
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@ -133,8 +133,10 @@ void Jit::CompileDelaySlot(bool saveFlags)
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if (saveFlags)
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SAVE_FLAGS; // preserve flag around the delay slot!
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js.inDelaySlot = true;
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u32 op = Memory::Read_Instruction(addr);
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MIPSCompileOp(op);
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js.inDelaySlot = false;
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FlushAll();
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if (saveFlags)
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