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ARM64: Start implementing soft-skinning. Disabled for now, needs work.
This commit is contained in:
Henrik Rydgård
Henrik Rydgard
parent
f82b613371
commit
597595f279
@ -985,7 +985,7 @@ void ARM64XEmitter::QuickCallFunction(ARM64Reg scratchreg, const void *func) {
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s64 distance = (s64)func - (s64)m_code;
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distance >>= 2; // Can only branch to opcode-aligned (4) addresses
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if (!IsInRangeImm26(distance)) {
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WARN_LOG(DYNA_REC, "Distance too far in function call (%p to %p)! Using scratch.", m_code, func);
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// WARN_LOG(DYNA_REC, "Distance too far in function call (%p to %p)! Using scratch.", m_code, func);
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MOVI2R(scratchreg, (uintptr_t)func);
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BLR(scratchreg);
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} else {
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@ -1090,14 +1090,14 @@ static void GetSystemReg(PStateField field, int &o0, int &op1, int &CRn, int &CR
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}
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void ARM64XEmitter::_MSR(PStateField field, ARM64Reg Rt) {
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int o0, op1, CRn, CRm, op2;
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int o0 = 0, op1 = 0, CRn = 0, CRm = 0, op2 = 0;
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_assert_msg_(JIT, Is64Bit(Rt), "MSR: Rt must be 64-bit");
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GetSystemReg(field, o0, op1, CRn, CRm, op2);
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EncodeSystemInst(o0, op1, CRn, CRm, op2, DecodeReg(Rt));
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}
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void ARM64XEmitter::MRS(ARM64Reg Rt, PStateField field) {
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int o0, op1, CRn, CRm, op2;
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int o0 = 0, op1 = 0, CRn = 0, CRm = 0, op2 = 0;
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_assert_msg_(JIT, Is64Bit(Rt), "MRS: Rt must be 64-bit");
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GetSystemReg(field, o0, op1, CRn, CRm, op2);
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EncodeSystemInst(o0 | 4, op1, CRn, CRm, op2, DecodeReg(Rt));
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@ -24,6 +24,9 @@
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#include "GPU/GPUState.h"
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#include "GPU/Common/VertexDecoderCommon.h"
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static float MEMORY_ALIGNED16(bones[16 * 8]); // First two are kept in registers
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static float MEMORY_ALIGNED16(boneMask[4]) = {1.0f, 1.0f, 1.0f, 0.0f};
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static const float by128 = 1.0f / 128.0f;
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static const float by16384 = 1.0f / 16384.0f;
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static const float by32768 = 1.0f / 32768.0f;
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@ -53,33 +56,31 @@ static const ARM64Reg fpUVoffsetReg = D1;
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static const ARM64Reg neonScratchReg = D2;
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static const ARM64Reg neonScratchReg2 = D3;
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static const ARM64Reg neonScratchRegQ = Q2;
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static const ARM64Reg neonUVScaleReg = D0;
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static const ARM64Reg neonUVOffsetReg = D1;
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// Everything above S6 is fair game for skinning. This means that we can easily fit four
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// full skin matrices in registers.
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static const ARM64Reg src[3] = {Q2, Q3, Q8};
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// S8-S15 are used during matrix generation
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static const ARM64Reg srcNEON = Q8;
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static const ARM64Reg accNEON = Q9;
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// These only live through the matrix multiplication
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static const ARM64Reg src[3] = { S16, S17, S18 }; // skin source
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static const ARM64Reg acc[3] = { S19, S20, S21 }; // skin accumulator
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static const ARM64Reg neonWeightRegsQ[2] = { Q2, Q3 };
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static const ARM64Reg srcNEON = Q2;
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static const ARM64Reg accNEON = Q3;
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// Q4-Q7 is the generated matrix that we multiply things by.
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// Q8,Q9 are accumulators/scratch for matrix mul.
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// Q10, Q11 are more scratch for matrix mul.
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// Q16+ are free-for-all for matrices. In 16 registers, we can fit 4 4x4 matrices.
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static const JitLookup jitLookup[] = {
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{&VertexDecoder::Step_WeightsU8, &VertexDecoderJitCache::Jit_WeightsU8},
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{&VertexDecoder::Step_WeightsU16, &VertexDecoderJitCache::Jit_WeightsU16},
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{&VertexDecoder::Step_WeightsFloat, &VertexDecoderJitCache::Jit_WeightsFloat},
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/*
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{&VertexDecoder::Step_WeightsU8Skin, &VertexDecoderJitCache::Jit_WeightsU8Skin},
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{&VertexDecoder::Step_WeightsU16Skin, &VertexDecoderJitCache::Jit_WeightsU16Skin},
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{&VertexDecoder::Step_WeightsFloatSkin, &VertexDecoderJitCache::Jit_WeightsFloatSkin},
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*/
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{&VertexDecoder::Step_TcU8, &VertexDecoderJitCache::Jit_TcU8},
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{&VertexDecoder::Step_TcU16, &VertexDecoderJitCache::Jit_TcU16},
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{&VertexDecoder::Step_TcFloat, &VertexDecoderJitCache::Jit_TcFloat},
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@ -95,11 +96,10 @@ static const JitLookup jitLookup[] = {
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{&VertexDecoder::Step_NormalS16, &VertexDecoderJitCache::Jit_NormalS16},
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{&VertexDecoder::Step_NormalFloat, &VertexDecoderJitCache::Jit_NormalFloat},
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/*
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{&VertexDecoder::Step_NormalS8Skin, &VertexDecoderJitCache::Jit_NormalS8Skin},
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{&VertexDecoder::Step_NormalS16Skin, &VertexDecoderJitCache::Jit_NormalS16Skin},
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{&VertexDecoder::Step_NormalFloatSkin, &VertexDecoderJitCache::Jit_NormalFloatSkin},
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*/
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{&VertexDecoder::Step_Color8888, &VertexDecoderJitCache::Jit_Color8888},
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/*
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{&VertexDecoder::Step_Color4444, &VertexDecoderJitCache::Jit_Color4444},
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@ -115,11 +115,12 @@ static const JitLookup jitLookup[] = {
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{&VertexDecoder::Step_PosS8, &VertexDecoderJitCache::Jit_PosS8},
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{&VertexDecoder::Step_PosS16, &VertexDecoderJitCache::Jit_PosS16},
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{&VertexDecoder::Step_PosFloat, &VertexDecoderJitCache::Jit_PosFloat},
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/*
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{&VertexDecoder::Step_PosS8Skin, &VertexDecoderJitCache::Jit_PosS8Skin},
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{&VertexDecoder::Step_PosS16Skin, &VertexDecoderJitCache::Jit_PosS16Skin},
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{&VertexDecoder::Step_PosFloatSkin, &VertexDecoderJitCache::Jit_PosFloatSkin},
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/*
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{&VertexDecoder::Step_NormalS8Morph, &VertexDecoderJitCache::Jit_NormalS8Morph},
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{&VertexDecoder::Step_NormalS16Morph, &VertexDecoderJitCache::Jit_NormalS16Morph},
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{&VertexDecoder::Step_NormalFloatMorph, &VertexDecoderJitCache::Jit_NormalFloatMorph},
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@ -183,9 +184,45 @@ JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec) {
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if (dec.weighttype && g_Config.bSoftwareSkinning && dec.morphcount == 1) {
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WARN_LOG(HLE, "vtxdec-arm64 does not support sw skinning");
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SetCodePtr(const_cast<u8 *>(start));
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return NULL;
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}
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// Add code to convert matrices to 4x4.
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// Later we might want to do this when the matrices are loaded instead.
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int boneCount = 0;
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if (dec.weighttype && g_Config.bSoftwareSkinning && dec.morphcount == 1) {
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// Copying from R3 to R4
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MOVP2R(X3, gstate.boneMatrix);
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MOVP2R(X4, bones);
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MOVP2R(X5, boneMask);
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fp.LDR(128, INDEX_UNSIGNED, Q3, X5, 0);
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for (int i = 0; i < 8; i++) {
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fp.LDR(128, INDEX_UNSIGNED, Q4, X3, 0); // Load 128 bits even though we just want 96
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fp.LDR(128, INDEX_UNSIGNED, Q5, X3, 12);
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fp.LDR(128, INDEX_UNSIGNED, Q6, X3, 24);
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fp.LDR(128, INDEX_UNSIGNED, Q7, X3, 36);
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fp.FMUL(32, Q4, Q4, Q3);
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fp.FMUL(32, Q5, Q5, Q3);
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fp.FMUL(32, Q6, Q6, Q6);
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fp.FMUL(32, Q7, Q7, Q7);
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// First four matrices are in registers.
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if (i < 4) {
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fp.FMOV((ARM64Reg)(Q16 + i * 4), Q4);
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fp.FMOV((ARM64Reg)(Q17 + i * 4), Q5);
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fp.FMOV((ARM64Reg)(Q18 + i * 4), Q6);
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fp.FMOV((ARM64Reg)(Q19 + i * 4), Q7);
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ADDI2R(X4, X4, 16 * 4);
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} else {
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fp.STR(128, INDEX_UNSIGNED, Q4, X4, 0);
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fp.STR(128, INDEX_UNSIGNED, Q5, X4, 16);
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fp.STR(128, INDEX_UNSIGNED, Q6, X4, 32);
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fp.STR(128, INDEX_UNSIGNED, Q7, X4, 48);
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ADDI2R(X4, X4, 16 * 4);
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}
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}
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}
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if (dec.col) {
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// Or LDB and skip the conditional? This is probably cheaper.
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MOVI2R(fullAlphaReg, 0xFF);
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@ -224,12 +261,12 @@ JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec) {
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char temp[1024] = { 0 };
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dec.ToString(temp);
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INFO_LOG(HLE, "=== %s (%d bytes) ===", temp, (int)(GetCodePtr() - start));
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ILOG("=== %s (%d bytes) ===", temp, (int)(GetCodePtr() - start));
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std::vector<std::string> lines = DisassembleArm64(start, GetCodePtr() - start);
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for (auto line : lines) {
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INFO_LOG(HLE, "%s", line.c_str());
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ILOG("%s", line.c_str());
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}
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INFO_LOG(HLE, "==========", temp);
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ILOG("==========", temp);
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return (JittedVertexDecoder)start;
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}
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@ -245,6 +282,56 @@ bool VertexDecoderJitCache::CompileStep(const VertexDecoder &dec, int step) {
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return false;
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}
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void VertexDecoderJitCache::Jit_ApplyWeights() {
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// We construct a matrix in Q4-Q7
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// We can use Q1 as temp.
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if (dec_->nweights >= 2) {
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MOVP2R(scratchReg, bones + 16 * 2);
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}
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for (int i = 0; i < dec_->nweights; i++) {
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switch (i) {
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case 0:
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fp.FMUL(32, Q4, Q16, neonWeightRegsQ[0], 0);
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fp.FMUL(32, Q5, Q17, neonWeightRegsQ[0], 0);
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fp.FMUL(32, Q6, Q18, neonWeightRegsQ[0], 0);
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fp.FMUL(32, Q7, Q19, neonWeightRegsQ[0], 0);
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break;
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case 1:
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fp.FMLA(32, Q4, Q20, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q5, Q21, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q6, Q22, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q7, Q23, neonWeightRegsQ[0], 1);
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break;
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case 2:
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fp.FMLA(32, Q4, Q24, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q5, Q25, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q6, Q26, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q7, Q27, neonWeightRegsQ[0], 1);
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break;
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case 3:
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fp.FMLA(32, Q4, Q28, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q5, Q29, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q6, Q30, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q7, Q31, neonWeightRegsQ[0], 1);
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break;
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default:
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// Matrices 2+ need to be loaded from memory.
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// Wonder if we can free up one more register so we could get some parallelism.
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// Actually Q3 is free if there are fewer than 5 weights...
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fp.LDP(INDEX_SIGNED, Q8, Q9, scratchReg, 0);
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fp.LDP(INDEX_SIGNED, Q10, Q11, scratchReg, 2 * 16);
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fp.FMLA(32, Q4, Q8, neonWeightRegsQ[i >> 2], i & 3);
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fp.FMLA(32, Q5, Q9, neonWeightRegsQ[i >> 2], i & 3);
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fp.FMLA(32, Q6, Q10, neonWeightRegsQ[i >> 2], i & 3);
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fp.FMLA(32, Q7, Q11, neonWeightRegsQ[i >> 2], i & 3);
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ADDI2R(scratchReg, scratchReg, 4 * 16);
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break;
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}
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}
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}
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void VertexDecoderJitCache::Jit_WeightsU8() {
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// Basic implementation - a byte at a time. TODO: Optimize
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int j;
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@ -294,6 +381,101 @@ void VertexDecoderJitCache::Jit_WeightsFloat() {
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}
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}
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void VertexDecoderJitCache::Jit_WeightsU8Skin() {
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// Weight is first so srcReg is correct.
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switch (dec_->nweights) {
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case 1: fp.LDR(8, INDEX_UNSIGNED, neonScratchReg, srcReg, 0); break;
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case 2: fp.LDR(16, INDEX_UNSIGNED, neonScratchReg, srcReg, 0); break;
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default:
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// For 3, we over read, for over 4, we read more later.
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fp.LDR(32, INDEX_UNSIGNED, neonScratchReg, srcReg, 0);
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break;
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}
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// TODO: Get rid of this constant, use fixed point conversion
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fp.MOVI2FDUP(Q3, by128, X0);
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fp.UXTL(8, neonScratchRegQ, neonScratchReg);
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fp.UXTL(16, neonScratchRegQ, neonScratchReg);
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fp.UCVTF(neonScratchRegQ, neonScratchRegQ);
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fp.FMUL(32, neonWeightRegsQ[0], neonScratchRegQ, Q3);
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if (dec_->nweights > 4) {
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switch (dec_->nweights) {
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case 5: fp.LDR(8, INDEX_UNSIGNED, neonScratchReg, srcReg, 4); break;
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case 6: fp.LDR(16, INDEX_UNSIGNED, neonScratchReg, srcReg, 4); break;
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case 7:
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case 8:
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fp.LDR(32, INDEX_UNSIGNED, neonScratchReg, srcReg, 4);
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break;
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}
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fp.UXTL(8, neonScratchRegQ, neonScratchReg);
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fp.UXTL(16, neonScratchRegQ, neonScratchReg);
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fp.UCVTF(neonScratchRegQ, neonScratchRegQ);
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fp.FMUL(32, neonWeightRegsQ[1], neonScratchRegQ, Q3);
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}
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Jit_ApplyWeights();
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}
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void VertexDecoderJitCache::Jit_WeightsU16Skin() {
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switch (dec_->nweights) {
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case 1: fp.LDR(16, INDEX_UNSIGNED, neonScratchReg, srcReg, 0); break;
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case 2: fp.LDR(32, INDEX_UNSIGNED, neonScratchReg, srcReg, 0); break;
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default:
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// For 3, we over read, for over 4, we read more later.
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fp.LDR(64, INDEX_UNSIGNED, neonScratchReg, srcReg, 0);
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break;
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}
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fp.MOVI2FDUP(Q3, by32768, X0);
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fp.UXTL(16, neonScratchRegQ, neonScratchReg);
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fp.UCVTF(neonScratchRegQ, neonScratchRegQ);
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fp.FMUL(32, neonWeightRegsQ[0], neonScratchRegQ, Q3);
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if (dec_->nweights > 4) {
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switch (dec_->nweights) {
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case 5: fp.LDR(16, INDEX_UNSIGNED, neonScratchReg, srcReg, 8); break;
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case 6: fp.LDR(32, INDEX_UNSIGNED, neonScratchReg, srcReg, 8); break;
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case 7:
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case 8:
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fp.LDR(64, INDEX_UNSIGNED, neonScratchReg, srcReg, 8);
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break;
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}
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fp.UXTL(16, neonScratchRegQ, neonScratchReg);
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fp.UCVTF(neonScratchRegQ, neonScratchRegQ);
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fp.FMUL(32, neonWeightRegsQ[1], neonScratchRegQ, Q3);
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}
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Jit_ApplyWeights();
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}
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void VertexDecoderJitCache::Jit_WeightsFloatSkin() {
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switch (dec_->nweights) {
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case 1:
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fp.LDR(32, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
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break;
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case 2:
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fp.LDR(64, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
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break;
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case 3:
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case 4:
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fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
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break;
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case 5:
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fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
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fp.LDR(32, INDEX_UNSIGNED, neonWeightRegsQ[1], srcReg, 16);
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break;
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case 6:
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fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
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fp.LDR(64, INDEX_UNSIGNED, neonWeightRegsQ[1], srcReg, 16);
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break;
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case 7:
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case 8:
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fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
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fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[1], srcReg, 16);
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break;
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}
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Jit_ApplyWeights();
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}
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void VertexDecoderJitCache::Jit_Color8888() {
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LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->coloff);
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// TODO: Set flags to determine if alpha != 0xFF.
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@ -445,6 +627,36 @@ void VertexDecoderJitCache::Jit_NormalFloat() {
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STR(INDEX_UNSIGNED, tempReg3, dstReg, dec_->decFmt.nrmoff + 8);
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}
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void VertexDecoderJitCache::Jit_NormalS8Skin() {
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Jit_AnyS8ToFloat(dec_->nrmoff);
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Jit_WriteMatrixMul(dec_->decFmt.nrmoff, false);
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}
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void VertexDecoderJitCache::Jit_NormalS16Skin() {
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Jit_AnyS16ToFloat(dec_->nrmoff);
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Jit_WriteMatrixMul(dec_->decFmt.nrmoff, false);
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}
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void VertexDecoderJitCache::Jit_NormalFloatSkin() {
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fp.LDR(128, INDEX_UNSIGNED, srcNEON, srcReg, dec_->nrmoff);
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Jit_WriteMatrixMul(dec_->decFmt.nrmoff, false);
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}
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void VertexDecoderJitCache::Jit_PosS8Skin() {
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Jit_AnyS8ToFloat(dec_->posoff);
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Jit_WriteMatrixMul(dec_->decFmt.posoff, true);
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}
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void VertexDecoderJitCache::Jit_PosS16Skin() {
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Jit_AnyS16ToFloat(dec_->posoff);
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Jit_WriteMatrixMul(dec_->decFmt.posoff, true);
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}
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void VertexDecoderJitCache::Jit_PosFloatSkin() {
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fp.LDR(128, INDEX_UNSIGNED, srcNEON, srcReg, dec_->posoff);
|
||||
Jit_WriteMatrixMul(dec_->decFmt.posoff, true);
|
||||
}
|
||||
|
||||
void VertexDecoderJitCache::Jit_AnyS8ToFloat(int srcoff) {
|
||||
// TODO: NEONize. In that case we'll leave all three floats in one register instead, so callers must change too.
|
||||
LDRSB(INDEX_UNSIGNED, tempReg1, srcReg, srcoff);
|
||||
@ -463,3 +675,14 @@ void VertexDecoderJitCache::Jit_AnyS16ToFloat(int srcoff) {
|
||||
fp.SCVTF(src[1], tempReg2, 15);
|
||||
fp.SCVTF(src[2], tempReg3, 15);
|
||||
}
|
||||
|
||||
void VertexDecoderJitCache::Jit_WriteMatrixMul(int outOff, bool pos) {
|
||||
// Multiply with the matrix sitting in Q4-Q7.
|
||||
fp.FMUL(32, accNEON, Q4, srcNEON, 0);
|
||||
fp.FMLA(32, accNEON, Q5, srcNEON, 1);
|
||||
fp.FMLA(32, accNEON, Q6, srcNEON, 2);
|
||||
if (pos) {
|
||||
fp.FADD(32, accNEON, accNEON, Q7);
|
||||
}
|
||||
fp.STR(128, INDEX_UNSIGNED, accNEON, dstReg, outOff);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user