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x86 jit: Rename BindToRegister to MapReg

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This commit is contained in:
Henrik Rydgard 2013-11-09 15:23:31 +01:00
parent d26692ef92
commit 5ad04a23f4
10 changed files with 78 additions and 77 deletions
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72
Core/MIPS/x86/CompALU.cpp
View File

@ -49,7 +49,7 @@ namespace MIPSComp
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
gpr.Lock(rt, rs);
gpr.BindToRegister(rt, rt == rs, true);
gpr.MapReg(rt, rt == rs, true);
if (rt != rs)
MOV(32, gpr.R(rt), gpr.R(rs));
(this->*arith)(32, gpr.R(rt), Imm32(uimm));
@ -82,7 +82,7 @@ namespace MIPSComp
}
gpr.Lock(rt, rs);
gpr.BindToRegister(rt, rt == rs, true);
gpr.MapReg(rt, rt == rs, true);
if (rt == rs || gpr.R(rs).IsSimpleReg())
LEA(32, gpr.RX(rt), MDisp(gpr.RX(rs), simm));
else
@ -104,8 +104,8 @@ namespace MIPSComp
}
gpr.Lock(rt, rs);
gpr.BindToRegister(rs, true, false);
gpr.BindToRegister(rt, rt == rs, true);
gpr.MapReg(rs, true, false);
gpr.MapReg(rt, rt == rs, true);
XOR(32, R(EAX), R(EAX));
CMP(32, gpr.R(rs), Imm32(simm));
SETcc(CC_L, R(EAX));
@ -121,8 +121,8 @@ namespace MIPSComp
}
gpr.Lock(rt, rs);
gpr.BindToRegister(rs, true, false);
gpr.BindToRegister(rt, rt == rs, true);
gpr.MapReg(rs, true, false);
gpr.MapReg(rt, rt == rs, true);
XOR(32, R(EAX), R(EAX));
CMP(32, gpr.R(rs), Imm32((u32)simm));
SETcc(CC_B, R(EAX));
@ -191,7 +191,7 @@ namespace MIPSComp
else
{
gpr.Lock(rd, rs);
gpr.BindToRegister(rd, rd == rs, true);
gpr.MapReg(rd, rd == rs, true);
BSR(32, EAX, gpr.R(rs));
FixupBranch notFound = J_CC(CC_Z);
@ -222,7 +222,7 @@ namespace MIPSComp
else
{
gpr.Lock(rd, rs);
gpr.BindToRegister(rd, rd == rs, true);
gpr.MapReg(rd, rd == rs, true);
MOV(32, R(EAX), gpr.R(rs));
NOT(32, R(EAX));
BSR(32, EAX, R(EAX));
@ -300,7 +300,7 @@ namespace MIPSComp
MIPSGPReg rsource = rt == MIPS_REG_ZERO ? rs : rt;
if (rsource != rd)
{
gpr.BindToRegister(rd, false, true);
gpr.MapReg(rd, false, true);
MOV(32, gpr.R(rd), gpr.R(rsource));
}
}
@ -309,7 +309,7 @@ namespace MIPSComp
{
// No temporary needed.
u32 rtval = gpr.GetImmediate32(rt);
gpr.BindToRegister(rd, rs == rd, true);
gpr.MapReg(rd, rs == rd, true);
if (rs != rd)
MOV(32, gpr.R(rd), gpr.R(rs));
(this->*arith)(32, gpr.R(rd), Imm32(rtval));
@ -319,7 +319,7 @@ namespace MIPSComp
// Use EAX as a temporary if we'd overwrite it.
if (rd == rt)
MOV(32, R(EAX), gpr.R(rt));
gpr.BindToRegister(rd, rs == rd, true);
gpr.MapReg(rd, rs == rd, true);
if (rs != rd)
MOV(32, gpr.R(rd), gpr.R(rs));
(this->*arith)(32, gpr.R(rd), rd == rt ? R(EAX) : gpr.R(rt));
@ -349,7 +349,7 @@ namespace MIPSComp
{
gpr.KillImmediate(rs, true, false);
// Need to load rd in case the condition fails.
gpr.BindToRegister(rd, true, true);
gpr.MapReg(rd, true, true);
CMP(32, gpr.R(rt), Imm32(0));
CMOVcc(32, gpr.RX(rd), gpr.R(rs), CC_E);
}
@ -360,7 +360,7 @@ namespace MIPSComp
gpr.SetImmediate32(rd, gpr.GetImmediate32(rs));
else if (rd != rs)
{
gpr.BindToRegister(rd, false, true);
gpr.MapReg(rd, false, true);
MOV(32, gpr.R(rd), gpr.R(rs));
}
}
@ -375,7 +375,7 @@ namespace MIPSComp
{
gpr.KillImmediate(rs, true, false);
// Need to load rd in case the condition fails.
gpr.BindToRegister(rd, true, true);
gpr.MapReg(rd, true, true);
CMP(32, gpr.R(rt), Imm32(0));
CMOVcc(32, gpr.RX(rd), gpr.R(rs), CC_NE);
}
@ -385,7 +385,7 @@ namespace MIPSComp
gpr.SetImmediate32(rd, gpr.GetImmediate32(rs));
else if (rd != rs)
{
gpr.BindToRegister(rd, false, true);
gpr.MapReg(rd, false, true);
MOV(32, gpr.R(rd), gpr.R(rs));
}
}
@ -424,8 +424,8 @@ namespace MIPSComp
else
{
gpr.Lock(rt, rs, rd);
gpr.BindToRegister(rs, true, false);
gpr.BindToRegister(rd, rd == rt, true);
gpr.MapReg(rs, true, false);
gpr.MapReg(rd, rd == rt, true);
XOR(32, R(EAX), R(EAX));
CMP(32, gpr.R(rs), gpr.R(rt));
SETcc(CC_L, R(EAX));
@ -440,8 +440,8 @@ namespace MIPSComp
else
{
gpr.Lock(rd, rs, rt);
gpr.BindToRegister(rs, true, false);
gpr.BindToRegister(rd, rd == rt, true);
gpr.MapReg(rs, true, false);
gpr.MapReg(rd, rd == rt, true);
XOR(32, R(EAX), R(EAX));
CMP(32, gpr.R(rs), gpr.R(rt));
SETcc(CC_B, R(EAX));
@ -458,7 +458,7 @@ namespace MIPSComp
MIPSGPReg rsrc = rd == rt ? rs : rt;
gpr.Lock(rd, rs, rt);
gpr.KillImmediate(rsrc, true, false);
gpr.BindToRegister(rd, rd == rs || rd == rt, true);
gpr.MapReg(rd, rd == rs || rd == rt, true);
if (rd != rt && rd != rs)
MOV(32, gpr.R(rd), gpr.R(rs));
CMP(32, gpr.R(rd), gpr.R(rsrc));
@ -475,7 +475,7 @@ namespace MIPSComp
MIPSGPReg rsrc = rd == rt ? rs : rt;
gpr.Lock(rd, rs, rt);
gpr.KillImmediate(rsrc, true, false);
gpr.BindToRegister(rd, rd == rs || rd == rt, true);
gpr.MapReg(rd, rd == rs || rd == rt, true);
if (rd != rt && rd != rs)
MOV(32, gpr.R(rd), gpr.R(rs));
CMP(32, gpr.R(rd), gpr.R(rsrc));
@ -524,7 +524,7 @@ namespace MIPSComp
}
gpr.Lock(rd, rt);
gpr.BindToRegister(rd, rd == rt, true);
gpr.MapReg(rd, rd == rt, true);
if (rd != rt)
MOV(32, gpr.R(rd), gpr.R(rt));
(this->*shift)(32, gpr.R(rd), Imm8(sa));
@ -548,7 +548,7 @@ namespace MIPSComp
if (gpr.IsImmediate(rs))
{
int sa = gpr.GetImmediate32(rs);
gpr.BindToRegister(rd, rd == rt, true);
gpr.MapReg(rd, rd == rt, true);
if (rd != rt)
MOV(32, gpr.R(rd), gpr.R(rt));
(this->*shift)(32, gpr.R(rd), Imm8(sa));
@ -556,7 +556,7 @@ namespace MIPSComp
else
{
gpr.FlushLockX(ECX);
gpr.BindToRegister(rd, rd == rt || rd == rs, true);
gpr.MapReg(rd, rd == rt || rd == rs, true);
MOV(32, R(ECX), gpr.R(rs)); // Only ECX can be used for variable shifts.
AND(32, R(ECX), Imm32(0x1f));
if (rd != rt)
@ -619,7 +619,7 @@ namespace MIPSComp
}
gpr.Lock(rs, rt);
gpr.BindToRegister(rt, rs == rt, true);
gpr.MapReg(rt, rs == rt, true);
if (rs != rt)
MOV(32, gpr.R(rt), gpr.R(rs));
SHR(32, gpr.R(rt), Imm8(pos));
@ -641,7 +641,7 @@ namespace MIPSComp
}
gpr.Lock(rs, rt);
gpr.BindToRegister(rt, true, true);
gpr.MapReg(rt, true, true);
AND(32, gpr.R(rt), Imm32(destmask));
OR(32, gpr.R(rt), Imm32(inserted));
gpr.UnlockAll();
@ -649,7 +649,7 @@ namespace MIPSComp
else
{
gpr.Lock(rs, rt);
gpr.BindToRegister(rt, true, true);
gpr.MapReg(rt, true, true);
MOV(32, R(EAX), gpr.R(rs));
AND(32, R(EAX), Imm32(sourcemask));
SHL(32, R(EAX), Imm8(pos));
@ -682,7 +682,7 @@ namespace MIPSComp
}
gpr.Lock(rd, rt);
gpr.BindToRegister(rd, rd == rt, true);
gpr.MapReg(rd, rd == rt, true);
#ifdef _M_IX86
// work around the byte-register addressing problem
if (!gpr.R(rt).IsSimpleReg(EDX) && !gpr.R(rt).IsSimpleReg(ECX))
@ -719,7 +719,7 @@ namespace MIPSComp
}
gpr.Lock(rd, rt);
gpr.BindToRegister(rd, rd == rt, true);
gpr.MapReg(rd, rd == rt, true);
if (rd != rt)
MOV(32, gpr.R(rd), gpr.R(rt));
@ -762,7 +762,7 @@ namespace MIPSComp
}
gpr.Lock(rd, rt);
gpr.BindToRegister(rd, rd == rt, true);
gpr.MapReg(rd, rd == rt, true);
MOVSX(32, 16, gpr.RX(rd), gpr.R(rt));
gpr.UnlockAll();
break;
@ -787,13 +787,13 @@ namespace MIPSComp
{
case 0xA0: //wsbh
gpr.Lock(rd, rt);
gpr.BindToRegister(rd, rd == rt, true);
gpr.MapReg(rd, rd == rt, true);
// Stub
gpr.UnlockAll();
break;
case 0xE0: //wsbw
gpr.Lock(rd, rt);
gpr.BindToRegister(rd, rd == rt, true);
gpr.MapReg(rd, rd == rt, true);
// Stub
gpr.UnlockAll();
break;
@ -813,22 +813,22 @@ namespace MIPSComp
switch (op & 63)
{
case 16: // R(rd) = HI; //mfhi
gpr.BindToRegister(rd, false, true);
gpr.MapReg(rd, false, true);
MOV(32, gpr.R(rd), M((void *)&mips_->hi));
break;
case 17: // HI = R(rs); //mthi
gpr.BindToRegister(rs, true, false);
gpr.MapReg(rs, true, false);
MOV(32, M((void *)&mips_->hi), gpr.R(rs));
break;
case 18: // R(rd) = LO; break; //mflo
gpr.BindToRegister(rd, false, true);
gpr.MapReg(rd, false, true);
MOV(32, gpr.R(rd), M((void *)&mips_->lo));
break;
case 19: // LO = R(rs); break; //mtlo
gpr.BindToRegister(rs, true, false);
gpr.MapReg(rs, true, false);
MOV(32, M((void *)&mips_->lo), gpr.R(rs));
break;

12
Core/MIPS/x86/CompBranch.cpp
View File

@ -186,7 +186,7 @@ void Jit::BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely)
}
else
{
gpr.BindToRegister(rs, true, false);
gpr.MapReg(rs, true, false);
CMP(32, gpr.R(rs), rt == MIPS_REG_ZERO ? Imm32(0) : gpr.R(rt));
}
@ -271,7 +271,7 @@ void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool li
CompileDelaySlot(DELAYSLOT_NICE);
if (andLink)
{
gpr.BindToRegister(MIPS_REG_RA, false, true);
gpr.MapReg(MIPS_REG_RA, false, true);
MOV(32, gpr.R(MIPS_REG_RA), Imm32(js.compilerPC + 8));
}
// Account for the increment in the loop.
@ -284,7 +284,7 @@ void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool li
if (!likely && delaySlotIsNice)
CompileDelaySlot(DELAYSLOT_NICE);
gpr.BindToRegister(rs, true, false);
gpr.MapReg(rs, true, false);
CMP(32, gpr.R(rs), Imm32(0));
Gen::FixupBranch ptr;
@ -550,7 +550,7 @@ void Jit::Comp_Jump(MIPSOpcode op)
break;
case 3: //jal
gpr.BindToRegister(MIPS_REG_RA, false, true);
gpr.MapReg(MIPS_REG_RA, false, true);
MOV(32, gpr.R(MIPS_REG_RA), Imm32(js.compilerPC + 8)); // Save return address
CompileDelaySlot(DELAYSLOT_NICE);
FlushAll();
@ -584,7 +584,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op)
if (IsSyscall(delaySlotOp))
{
// If this is a syscall, write the pc (for thread switching and other good reasons.)
gpr.BindToRegister(rs, true, false);
gpr.MapReg(rs, true, false);
MOV(32, M(&currentMIPS->pc), gpr.R(rs));
CompileDelaySlot(DELAYSLOT_FLUSH);
@ -613,7 +613,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op)
else
{
// Latch destination now - save it in memory.
gpr.BindToRegister(rs, true, false);
gpr.MapReg(rs, true, false);
MOV(32, M(&savedPC), gpr.R(rs));
CompileDelaySlot(DELAYSLOT_NICE);
MOV(32, R(EAX), M(&savedPC));

29
Core/MIPS/x86/CompFPU.cpp
View File

@ -53,21 +53,21 @@ void Jit::CompFPTriArith(MIPSOpcode op, void (XEmitter::*arith)(X64Reg reg, OpAr
if (fs == fd)
{
fpr.BindToRegister(fd, true, true);
fpr.MapReg(fd, true, true);
(this->*arith)(fpr.RX(fd), fpr.R(ft));
}
else if (ft == fd && !orderMatters)
{
fpr.BindToRegister(fd, true, true);
fpr.MapReg(fd, true, true);
(this->*arith)(fpr.RX(fd), fpr.R(fs));
}
else if (ft != fd && fs != fd && ft != fs) {
fpr.BindToRegister(fd, false, true);
fpr.MapReg(fd, false, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
(this->*arith)(fpr.RX(fd), fpr.R(ft));
}
else {
fpr.BindToRegister(fd, true, true);
fpr.MapReg(fd, true, true);
MOVSS(XMM0, fpr.R(fs));
(this->*arith)(XMM0, fpr.R(ft));
MOVSS(fpr.RX(fd), R(XMM0));
@ -105,7 +105,7 @@ void Jit::Comp_FPULS(MIPSOpcode op)
{
gpr.Lock(rs);
fpr.SpillLock(ft);
fpr.BindToRegister(ft, false, true);
fpr.MapReg(ft, false, true);
JitSafeMem safe(this, rs, offset);
OpArg src;
@ -126,7 +126,7 @@ void Jit::Comp_FPULS(MIPSOpcode op)
{
gpr.Lock(rs);
fpr.SpillLock(ft);
fpr.BindToRegister(ft, true, false);
fpr.MapReg(ft, true, false);
JitSafeMem safe(this, rs, offset);
OpArg dest;
@ -238,7 +238,7 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
{
case 5: //F(fd) = fabsf(F(fs)); break; //abs
fpr.SpillLock(fd, fs);
fpr.BindToRegister(fd, fd == fs, true);
fpr.MapReg(fd, fd == fs, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
PAND(fpr.RX(fd), M((void *)ssNoSignMask));
fpr.ReleaseSpillLocks();
@ -247,7 +247,7 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
case 6: //F(fd) = F(fs); break; //mov
if (fd != fs) {
fpr.SpillLock(fd, fs);
fpr.BindToRegister(fd, fd == fs, true);
fpr.MapReg(fd, fd == fs, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
fpr.ReleaseSpillLocks();
}
@ -255,7 +255,7 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
case 7: //F(fd) = -F(fs); break; //neg
fpr.SpillLock(fd, fs);
fpr.BindToRegister(fd, fd == fs, true);
fpr.MapReg(fd, fd == fs, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
PXOR(fpr.RX(fd), M((void *)ssSignBits2));
fpr.ReleaseSpillLocks();
@ -264,7 +264,7 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
fpr.SpillLock(fd, fs); // this probably works, just badly tested
fpr.BindToRegister(fd, fd == fs, true);
fpr.MapReg(fd, fd == fs, true);
SQRTSS(fpr.RX(fd), fpr.R(fs));
fpr.ReleaseSpillLocks();
return;
@ -294,6 +294,7 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
break;
case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
// Store to memory so we can read it as an integer value.
fpr.StoreFromRegister(fs);
CVTSI2SS(XMM0, fpr.R(fs));
MOVSS(fpr.R(fd), XMM0);
@ -320,8 +321,8 @@ void Jit::Comp_mxc1(MIPSOpcode op)
{
case 0: // R(rt) = FI(fs); break; //mfc1
if (rt != MIPS_REG_ZERO) {
fpr.BindToRegister(fs, true, false); // TODO: Seems the V register becomes dirty here? It shouldn't.
gpr.BindToRegister(rt, false, true);
fpr.MapReg(fs, true, false); // TODO: Seems the V register becomes dirty here? It shouldn't.
gpr.MapReg(rt, false, true);
MOVD_xmm(gpr.R(rt), fpr.RX(fs));
}
break;
@ -331,8 +332,8 @@ void Jit::Comp_mxc1(MIPSOpcode op)
return;
case 4: //FI(fs) = R(rt); break; //mtc1
gpr.BindToRegister(rt, true, false);
fpr.BindToRegister(fs, false, true); // TODO: Seems the V register becomes dirty here? It shouldn't.
gpr.MapReg(rt, true, false);
fpr.MapReg(fs, false, true); // TODO: Seems the V register becomes dirty here? It shouldn't.
MOVD_xmm(fpr.RX(fs), gpr.R(rt));
return;

6
Core/MIPS/x86/CompLoadStore.cpp
View File

@ -52,7 +52,7 @@ namespace MIPSComp
MIPSGPReg rs = _RS;
gpr.Lock(rt, rs);
gpr.BindToRegister(rt, rt == rs, true);
gpr.MapReg(rt, rt == rs, true);
JitSafeMem safe(this, rs, offset);
OpArg src;
@ -73,7 +73,7 @@ namespace MIPSComp
MIPSGPReg rs = _RS;
gpr.Lock(rt, rs);
gpr.BindToRegister(rt, true, false);
gpr.MapReg(rt, true, false);
#ifdef _M_IX86
// We use EDX so we can have DL for 8-bit ops.
@ -122,7 +122,7 @@ namespace MIPSComp
#endif
gpr.Lock(rt);
gpr.BindToRegister(rt, true, !isStore);
gpr.MapReg(rt, true, !isStore);
// Grab the offset from alignment for shifting (<< 3 for bytes -> bits.)
MOV(32, R(shiftReg), gpr.R(rs));

18
Core/MIPS/x86/CompVFPU.cpp
View File

@ -213,7 +213,7 @@ void Jit::Comp_SV(MIPSOpcode op) {
{
case 50: //lv.s // VI(vt) = Memory::Read_U32(addr);
{
gpr.BindToRegister(rs, true, false);
gpr.MapReg(rs, true, false);
fpr.MapRegV(vt, MAP_NOINIT);
JitSafeMem safe(this, rs, imm);
@ -237,7 +237,7 @@ void Jit::Comp_SV(MIPSOpcode op) {
case 58: //sv.s // Memory::Write_U32(VI(vt), addr);
{
gpr.BindToRegister(rs, true, true);
gpr.MapReg(rs, true, true);
// Even if we don't use real SIMD there's still 8 or 16 scalar float registers.
fpr.MapRegV(vt, 0);
@ -283,7 +283,7 @@ void Jit::Comp_SVQ(MIPSOpcode op)
}
DISABLE;
gpr.BindToRegister(rs, true, true);
gpr.MapReg(rs, true, true);
gpr.FlushLockX(ECX);
u8 vregs[4];
GetVectorRegs(vregs, V_Quad, vt);
@ -345,7 +345,7 @@ void Jit::Comp_SVQ(MIPSOpcode op)
case 54: //lv.q
{
gpr.BindToRegister(rs, true, true);
gpr.MapReg(rs, true, true);
u8 vregs[4];
GetVectorRegs(vregs, V_Quad, vt);
@ -378,7 +378,7 @@ void Jit::Comp_SVQ(MIPSOpcode op)
case 62: //sv.q
{
gpr.BindToRegister(rs, true, true);
gpr.MapReg(rs, true, true);
u8 vregs[4];
GetVectorRegs(vregs, V_Quad, vt);
@ -1557,12 +1557,12 @@ void Jit::Comp_Mftv(MIPSOpcode op) {
if (rt != MIPS_REG_ZERO) {
if (imm < 128) { //R(rt) = VI(imm);
fpr.MapRegV(imm, 0); // TODO: Seems the V register becomes dirty here? It shouldn't.
gpr.BindToRegister(rt, false, true);
gpr.MapReg(rt, false, true);
MOVD_xmm(gpr.R(rt), fpr.VX(imm));
} else if (imm < 128 + VFPU_CTRL_MAX) { //mfvc
// In case we have a saved prefix.
FlushPrefixV();
gpr.BindToRegister(rt, false, true);
gpr.MapReg(rt, false, true);
MOV(32, gpr.R(rt), M(&currentMIPS->vfpuCtrl[imm - 128]));
} else {
//ERROR - maybe need to make this value too an "interlock" value?
@ -1574,10 +1574,10 @@ void Jit::Comp_Mftv(MIPSOpcode op) {
case 7: //mtv
if (imm < 128) { // VI(imm) = R(rt);
fpr.MapRegV(imm, MAP_DIRTY | MAP_NOINIT); // TODO: Seems the V register becomes dirty here? It shouldn't.
gpr.BindToRegister(rt, true, false);
gpr.MapReg(rt, true, false);
MOVD_xmm(fpr.VX(imm), gpr.R(rt));
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc //currentMIPS->vfpuCtrl[imm - 128] = R(rt);
gpr.BindToRegister(rt, true, false);
gpr.MapReg(rt, true, false);
MOV(32, M(&currentMIPS->vfpuCtrl[imm - 128]), gpr.R(rt));
// TODO: Optimization if rt is Imm?

2
Core/MIPS/x86/Jit.cpp
View File

@ -621,7 +621,7 @@ OpArg Jit::JitSafeMem::PrepareMemoryOpArg(ReadType type)
if (jit_->gpr.R(raddr_).IsSimpleReg() && !needTemp)
{
jit_->gpr.BindToRegister(raddr_, true, false);
jit_->gpr.MapReg(raddr_, true, false);
xaddr_ = jit_->gpr.RX(raddr_);
}
else

4
Core/MIPS/x86/RegCache.cpp
View File

@ -219,13 +219,13 @@ OpArg GPRRegCache::GetDefaultLocation(MIPSGPReg reg) const {
void GPRRegCache::KillImmediate(MIPSGPReg preg, bool doLoad, bool makeDirty) {
if (regs[preg].away) {
if (regs[preg].location.IsImm())
BindToRegister(preg, doLoad, makeDirty);
MapReg(preg, doLoad, makeDirty);
else if (regs[preg].location.IsSimpleReg())
xregs[RX(preg)].dirty |= makeDirty;
}
}
void GPRRegCache::BindToRegister(MIPSGPReg i, bool doLoad, bool makeDirty) {
void GPRRegCache::MapReg(MIPSGPReg i, bool doLoad, bool makeDirty) {
if (!regs[i].away && regs[i].location.IsImm())
PanicAlert("Bad immediate");

2
Core/MIPS/x86/RegCache.h
View File

@ -74,7 +74,7 @@ public:
int SanityCheck() const;
void KillImmediate(MIPSGPReg preg, bool doLoad, bool makeDirty);
void BindToRegister(MIPSGPReg preg, bool doLoad = true, bool makeDirty = true);
void MapReg(MIPSGPReg preg, bool doLoad = true, bool makeDirty = true);
void StoreFromRegister(MIPSGPReg preg);
const OpArg &R(MIPSGPReg preg) const {return regs[preg].location;}

8
Core/MIPS/x86/RegCacheFPU.cpp
View File

@ -78,7 +78,7 @@ void FPURegCache::SpillLockV(int vec, VectorSize sz) {
}
void FPURegCache::MapRegV(int vreg, int flags) {
BindToRegister(vreg + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0);
MapReg(vreg + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0);
}
void FPURegCache::MapRegsV(int vec, VectorSize sz, int flags) {
@ -86,14 +86,14 @@ void FPURegCache::MapRegsV(int vec, VectorSize sz, int flags) {
GetVectorRegs(v, sz, vec);
SpillLockV(v, sz);
for (int i = 0; i < GetNumVectorElements(sz); i++) {
BindToRegister(v[i] + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0);
MapReg(v[i] + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0);
}
}
void FPURegCache::MapRegsV(const u8 *v, VectorSize sz, int flags) {
SpillLockV(v, sz);
for (int i = 0; i < GetNumVectorElements(sz); i++) {
BindToRegister(v[i] + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0);
MapReg(v[i] + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0);
}
}
@ -109,7 +109,7 @@ void FPURegCache::ReleaseSpillLocks() {
DiscardR(i);
}
void FPURegCache::BindToRegister(const int i, bool doLoad, bool makeDirty) {
void FPURegCache::MapReg(const int i, bool doLoad, bool makeDirty) {
_assert_msg_(JIT, !regs[i].location.IsImm(), "WTF - load - imm");
if (!regs[i].away) {
// Reg is at home in the memory register file. Let's pull it out.

2
Core/MIPS/x86/RegCacheFPU.h
View File

@ -88,7 +88,7 @@ public:
~FPURegCache() {}
void Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats);
void BindToRegister(int preg, bool doLoad = true, bool makeDirty = true);
void MapReg(int preg, bool doLoad = true, bool makeDirty = true);
void StoreFromRegister(int preg);
void StoreFromRegisterV(int preg) {
StoreFromRegister(preg + 32);