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Unlock the other 16 regs that are available for NEON.

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This commit is contained in:
Sacha 2013-06-09 23:15:59 +10:00
parent 29d1e40c79
commit 637d75f47d
2 changed files with 4 additions and 5 deletions
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3
Common/ArmEmitter.cpp
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@ -137,7 +137,7 @@ void ARMXEmitter::MOVI2F(ARMReg dest, float val, ARMReg tempReg, bool negate)
u32 imm8 = (conv.u & 0x80000000) >> 24; // sign bit
imm8 |= (!bit6 << 6);
imm8 |= (conv.u & 0x1F80000) >> 19;
VMOV(dest, Operand2(imm8, TYPE_IMM));
VMOV(dest, IMM(imm8));
return;
}
}
@ -1107,7 +1107,6 @@ void ARMXEmitter::VMOV(ARMReg Dest, Operand2 op2)
{
_assert_msg_(DYNA_REC, cpu_info.bVFPv3, "VMOV #imm requires VFPv3");
Write32(condition | (0xEB << 20) | EncodeVd(Dest) | (0xA << 8) | op2.Imm8VFP());
fprintf(stderr, "Encoding: %x\n", condition | (0xEB << 20) | EncodeVd(Dest) | (0xB << 8) | op2.Imm8VFP());
}
void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high)
{

6
Core/MIPS/ARM/ArmRegCacheFPU.cpp
View File

@ -16,6 +16,7 @@
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "Common/ArmEmitter.h"
#include "Common/CPUDetect.h"
#include "Core/MIPS/ARM/ArmRegCacheFPU.h"
@ -48,13 +49,12 @@ static const ARMReg *GetMIPSAllocationOrder(int &count) {
static const ARMReg allocationOrder[] = {
S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
};
// With NEON, we'll have many more.
// With NEON, we have many more.
static const ARMReg allocationOrderNEON[] = {
S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15,
S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31
};
bool useNEON = false; // TODO: Use cpu detect
if (useNEON) {
if (cpu_info.bNEON) {
count = sizeof(allocationOrderNEON) / sizeof(const int);
return allocationOrderNEON;
} else {