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jit-ir: Enable IR for madd(u)/msub(u).

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This commit is contained in:
Unknown W. Brackets 2016-05-14 18:46:55 -07:00
parent a05ae2a0a6
commit 6413b44434
3 changed files with 38 additions and 4 deletions
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4
Core/MIPS/IR/IRCompALU.cpp
View File

@ -358,22 +358,18 @@ void IRFrontend::Comp_MulDivType(MIPSOpcode op) {
break;
case 28: //madd
DISABLE;
ir.Write(IROp::Madd, 0, rs, rt);
break;
case 29: //maddu
DISABLE;
ir.Write(IROp::MaddU, 0, rs, rt);
break;
case 46: // msub
DISABLE;
ir.Write(IROp::Msub, 0, rs, rt);
break;
case 47: // msubu
DISABLE;
ir.Write(IROp::MsubU, 0, rs, rt);
break;

32
Core/MIPS/IR/IRInterpreter.cpp
View File

@ -405,6 +405,38 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
memcpy(&mips->lo, &result, 8);
break;
}
case IROp::Madd:
{
s64 result;
memcpy(&result, &mips->lo, 8);
result += (s64)(s32)mips->r[inst->src1] * (s64)(s32)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
break;
}
case IROp::MaddU:
{
s64 result;
memcpy(&result, &mips->lo, 8);
result += (u64)mips->r[inst->src1] * (u64)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
break;
}
case IROp::Msub:
{
s64 result;
memcpy(&result, &mips->lo, 8);
result -= (s64)(s32)mips->r[inst->src1] * (s64)(s32)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
break;
}
case IROp::MsubU:
{
s64 result;
memcpy(&result, &mips->lo, 8);
result -= (u64)mips->r[inst->src1] * (u64)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
break;
}
case IROp::BSwap16:
{

6
Core/MIPS/IR/IRPassSimplify.cpp
View File

@ -350,6 +350,12 @@ bool PropagateConstants(const IRWriter &in, IRWriter &out) {
case IROp::Mult:
case IROp::MultU:
case IROp::Madd:
case IROp::MaddU:
case IROp::Msub:
case IROp::MsubU:
case IROp::Div:
case IROp::DivU:
gpr.MapInIn(inst.src1, inst.src2);
goto doDefault;