libretro/ppsspp
1
0
Fork 0
mirror of https://github.com/libretro/ppsspp.git synced 2024-11-30 03:40:32 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Implement sc/ll (llbit is not cleared correctly though)

Browse Source
This commit is contained in:
Henrik Rydgard 2012-11-07 17:34:25 +01:00
parent 3ed790e6a3
commit 7385113948
5 changed files with 33 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Core/MIPS/MIPS.cpp
View File

@ -87,6 +87,7 @@ void MIPSState::Reset()
exceptions = 0;
currentMIPS = this;
inDelaySlot = false;
llBit = 0;
nextPC = 0;
// Initialize the VFPU random number generator with .. something?
rng.Init(0x1337);

1
Core/MIPS/MIPS.h
View File

@ -124,6 +124,7 @@ public:
GMRng rng; // VFPU hardware random number generator. Probably not the right type.
bool inDelaySlot;
int llBit; // ll/sc
CPUType cpuType;

29
Core/MIPS/MIPSInt.cpp
View File

@ -109,7 +109,7 @@ namespace MIPSInt
{
void Int_Cache(u32 op)
{
DEBUG_LOG(CPU,"cache instruction %08x",op);
// DEBUG_LOG(CPU,"cache instruction %08x",op);
PC += 4;
}
@ -301,6 +301,33 @@ namespace MIPSInt
PC += 4;
}
void Int_StoreSync(u32 op)
{
s32 imm = (signed short)(op&0xFFFF);
int base = ((op >> 21) & 0x1f);
int rt = (op >> 16) & 0x1f;
u32 addr = R(base) + imm;
switch (op >> 26)
{
case 48: // ll
R(rt) = Memory::Read_U32(addr);
currentMIPS->llBit = 1;
break;
case 56: // sc
if (currentMIPS->llBit) {
Memory::Write_U32(R(rt), addr);
R(rt) = 1;
} else {
R(rt) = 0;
}
break;
default:
_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
break;
}
PC += 4;
}
void Int_RType3(u32 op)

1
Core/MIPS/MIPSInt.h
View File

@ -53,4 +53,5 @@ namespace MIPSInt
void Int_Cache(u32 op);
void Int_Sync(u32 op);
void Int_Break(u32 op);
void Int_StoreSync(u32 op);
}

4
Core/MIPS/MIPSTables.cpp
View File

@ -148,7 +148,7 @@ const MIPSInstruction tableImmediate[64] = //xxxxxx .....
INSTR("swr", &Jit::Comp_ITypeMem, Dis_ITypeMem, Int_ITypeMem, IN_IMM16|IN_RS_ADDR|IN_RT|OUT_MEM),
INSTR("cache", &Jit::Comp_Generic, Dis_Generic, Int_Cache, 0),
//48
INSTR("ll", &Jit::Comp_Generic, Dis_Generic, 0, 0),
INSTR("ll", &Jit::Comp_Generic, Dis_Generic, Int_StoreSync, 0),
INSTR("lwc1", &Jit::Comp_FPULS, Dis_FPULS, Int_FPULS, IN_RT|IN_RS_ADDR),
INSTR("lv.s", &Jit::Comp_Generic, Dis_SV, Int_SV, IS_VFPU),
{-2}, // HIT THIS IN WIPEOUT
@ -157,7 +157,7 @@ const MIPSInstruction tableImmediate[64] = //xxxxxx .....
INSTR("lv.q", &Jit::Comp_Generic, Dis_SVQ, Int_SVQ, IS_VFPU), //copU
{VFPU5},
//56
INSTR("sc", &Jit::Comp_Generic, Dis_Generic, 0, 0),
INSTR("sc", &Jit::Comp_Generic, Dis_Generic, Int_StoreSync, 0),
INSTR("swc1", &Jit::Comp_FPULS, Dis_FPULS, Int_FPULS, 0), //copU
INSTR("sv.s", &Jit::Comp_Generic, Dis_SV, Int_SV,IS_VFPU),
{-2},