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Resurrect vmfvc/vmtvc, they are different from mfvc/mtvc

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This commit is contained in:
Henrik Rydgard 2012-11-22 22:26:13 +01:00
parent 1e68757089
commit 772b599041
3 changed files with 26 additions and 6 deletions
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2
Core/MIPS/MIPSDisVFPU.cpp
View File

@ -287,7 +287,7 @@ namespace MIPSDis
void Dis_Vflush(u32 op, char *out)
{
sprintf(out,"vflush\tand friends");
sprintf(out,"vflush");
}
void Dis_Vcrs(u32 op, char *out)

26
Core/MIPS/MIPSIntVFPU.cpp
View File

@ -1110,26 +1110,28 @@ namespace MIPSInt
int rt = _RT;
switch ((op >> 21) & 0x1f)
{
case 3: //mfv
case 3: //mfv / mfvc
if (imm < 128) {
R(rt) = VI(imm);
} else if (imm < 128 + VFPU_CTRL_MAX) {
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc
R(rt) = currentMIPS->vfpuCtrl[imm - 128];
} else {
//ERROR
_dbg_assert_msg_(CPU,0,"mfv - invalid register");
}
break;
case 7: //mtv
if (imm < 128) {
VI(imm) = R(rt);
} else if (imm < 128 + VFPU_CTRL_MAX) {
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc
currentMIPS->vfpuCtrl[imm - 128] = R(rt);
} else {
//ERROR
_dbg_assert_msg_(CPU,0,"mtv - invalid register");
}
break;
default:
_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
break;
@ -1137,6 +1139,24 @@ namespace MIPSInt
PC += 4;
}
void Int_Vmfvc(u32 op) {
int vs = _VS;
int imm = op & 0xFF;
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
VI(vs) = currentMIPS->vfpuCtrl[imm - 128];
}
PC += 4;
}
void Int_Vmtvc(u32 op) {
int vs = _VS;
int imm = op & 0xFF;
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
currentMIPS->vfpuCtrl[imm - 128] = VI(vs);
}
PC += 4;
}
#undef max
void Int_Vcst(u32 op)

4
Core/MIPS/MIPSTables.cpp
View File

@ -709,8 +709,8 @@ MIPSInstruction tableVFPU9[32] = //110100 00010 xxxxx
{-2},
//16
{-2}, //INSTR("vmfvc", &Jit::Comp_Generic, Dis_Generic, Int_Vmfvc, IS_VFPU), MUST BE WRONG, covered by mfv
{-2}, //INSTR("vmtvc", &Jit::Comp_Generic, Dis_Generic, Int_Vmtvc, IS_VFPU),
INSTR("vmfvc", &Jit::Comp_Generic, Dis_Generic, Int_Vmfvc, IS_VFPU),
INSTR("vmtvc", &Jit::Comp_Generic, Dis_Generic, Int_Vmtvc, IS_VFPU),
{-2},
{-2},