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Enable the new vreg flushing mechanism on ARM.
Reduce logspam seen in a couple games.
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@ -152,7 +152,7 @@ public:
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//if(dl->status < 0 || dl->status > PSP_GE_LIST_PAUSED)
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// ERROR_LOG(SCEGE, "Weird DL status after signal suspend %x", dl->status);
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if (newState != PSP_GE_DL_STATE_RUNNING)
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INFO_LOG_REPORT(SCEGE, "GE Interrupt: newState might be %d", newState);
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DEBUG_LOG_REPORT(SCEGE, "GE Interrupt: newState might be %d", newState);
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dl->state = PSP_GE_DL_STATE_RUNNING;
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}
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@ -333,14 +333,12 @@ void ArmRegCacheFPU::FlushAll() {
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DiscardR(i);
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}
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#if 0
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// Loop through the ARM registers, then use GetMipsRegOffset to determine if MIPS registers are
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// sequential. This is necessary because we store VFPU registers in a staggered order to get
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// columns sequential (most VFPU math in nearly all games is in columns, not rows).
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int numArmRegs;
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// We rely on the allocation order being sequental.
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// We rely on the allocation order being sequential.
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const ARMReg baseReg = GetMIPSAllocationOrder(numArmRegs)[0];
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for (int i = 0; i < numArmRegs; i++) {
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@ -357,6 +355,11 @@ void ArmRegCacheFPU::FlushAll() {
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if (c == 1) {
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// ILOG("Got single register: %i (%i)", a, m);
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emit_->VSTR((ARMReg)(a + S0), CTXREG, GetMipsRegOffset(m));
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} else if (c == 2) {
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// Probably not worth using VSTMIA for two.
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int offset = GetMipsRegOffset(m);
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emit_->VSTR((ARMReg)(a + S0), CTXREG, offset);
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emit_->VSTR((ARMReg)(a + 1 + S0), CTXREG, offset + 4);
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} else {
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// ILOG("Got sequence: %i at %i (%i)", c, a, m);
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emit_->ADDI2R(R0, CTXREG, GetMipsRegOffset(m), R1);
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@ -382,11 +385,6 @@ void ArmRegCacheFPU::FlushAll() {
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// already not dirty
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}
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}
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#else
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for (int i = 0; i < NUM_MIPSFPUREG; i++) {
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FlushR(i);
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}
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#endif
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// Sanity check
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for (int i = 0; i < numARMFpuReg_; i++) {
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@ -428,7 +426,6 @@ void ArmRegCacheFPU::DiscardR(MIPSReg r) {
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mr[r].spillLock = false;
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}
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bool ArmRegCacheFPU::IsTempX(ARMReg r) const {
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return ar[r - S0].mipsReg >= TEMP0;
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}
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