From 81589b67e582dc5e68e70460d33e5f6b28ae0679 Mon Sep 17 00:00:00 2001
From: Henrik Rydgard <hrydgard@gmail.com>
Date: Fri, 15 Feb 2013 23:33:35 +0100
Subject: [PATCH] Save one instruction on jal, shorten block exits by one
 instruction (moved to dispatcher).

---
 Core/MIPS/ARM/ArmAsm.cpp        | 3 +++
 Core/MIPS/ARM/ArmCompBranch.cpp | 9 +++------
 Core/MIPS/ARM/ArmCompVFPU.cpp   | 2 ++
 Core/MIPS/ARM/ArmJit.cpp        | 3 +--
 Core/MIPS/ARM/ArmJit.h          | 1 +
 5 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/Core/MIPS/ARM/ArmAsm.cpp b/Core/MIPS/ARM/ArmAsm.cpp
index 95be71b9e..bd0c4af4a 100644
--- a/Core/MIPS/ARM/ArmAsm.cpp
+++ b/Core/MIPS/ARM/ArmAsm.cpp
@@ -140,6 +140,9 @@ void Jit::GenerateFixedCode()
 		FixupBranch badCoreState = B_CC(CC_NEQ);
 		FixupBranch skipToRealDispatch2 = B(); //skip the sync and compare first time
 
+		dispatcherPCInR0 = GetCodePtr();
+		MovToPC(R0);
+
 		// At this point : flags = EQ. Fine for the next check, no need to jump over it.
 		dispatcher = GetCodePtr();
 
diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp
index c36b6111b..bd5eed47c 100644
--- a/Core/MIPS/ARM/ArmCompBranch.cpp
+++ b/Core/MIPS/ARM/ArmCompBranch.cpp
@@ -146,9 +146,8 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely
 	// Take the branch
 	if (andLink)
 	{
-		ADD(R1, R10, MIPS_REG_RA * 4);  // compute address of RA in ram
 		MOVI2R(R0, js.compilerPC + 8);
-		STR(R1, R0);
+		STR(CTXREG, R0, MIPS_REG_RA * 4);
 	}
 
 	WriteExit(targetAddr, 0);
@@ -340,9 +339,8 @@ void Jit::Comp_Jump(u32 op)
     break; 
 
 	case 3: //jal
-		ADD(R1, R10, MIPS_REG_RA * 4);  // compute address of RA in ram
 		MOVI2R(R0, js.compilerPC + 8);
-		STR(R1, R0);
+		STR(CTXREG, R0, MIPS_REG_RA * 4);
 		WriteExit(targetAddr, 0);
 		break;
 
@@ -389,9 +387,8 @@ void Jit::Comp_JumpReg(u32 op)
 	case 8: //jr
 		break;
 	case 9: //jalr
-		ADD(R1, R10, MIPS_REG_RA * 4);  // compute address of RA in ram
 		MOVI2R(R0, js.compilerPC + 8);
-		STR(R1, R0);
+		STR(CTXREG, R0, MIPS_REG_RA * 4);
 		break;
 	default:
 		_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
diff --git a/Core/MIPS/ARM/ArmCompVFPU.cpp b/Core/MIPS/ARM/ArmCompVFPU.cpp
index 63e7b0185..d6c378f47 100644
--- a/Core/MIPS/ARM/ArmCompVFPU.cpp
+++ b/Core/MIPS/ARM/ArmCompVFPU.cpp
@@ -68,6 +68,8 @@ namespace MIPSComp
 
 		case 62: //sv.q
 			{
+				DISABLE;
+
 				gpr.MapReg(rs);
 				SetR0ToEffectiveAddress(rs, imm);
 
diff --git a/Core/MIPS/ARM/ArmJit.cpp b/Core/MIPS/ARM/ArmJit.cpp
index 2b0931167..93aee6925 100644
--- a/Core/MIPS/ARM/ArmJit.cpp
+++ b/Core/MIPS/ARM/ArmJit.cpp
@@ -293,8 +293,7 @@ void Jit::WriteExit(u32 destination, int exit_num)
 		b->linkStatus[exit_num] = true;
 	} else {
 		MOVI2R(R0, destination);
-		MovToPC(R0);
-		B((const void *)dispatcher);	
+		B((const void *)dispatcherPCInR0);	
 	}
 }
 
diff --git a/Core/MIPS/ARM/ArmJit.h b/Core/MIPS/ARM/ArmJit.h
index b7a5aebe9..9e8365ef5 100644
--- a/Core/MIPS/ARM/ArmJit.h
+++ b/Core/MIPS/ARM/ArmJit.h
@@ -219,6 +219,7 @@ public:
 	const u8 *outerLoop;
 	const u8 *outerLoopPCInR0;
 	const u8 *dispatcherCheckCoreState;
+	const u8 *dispatcherPCInR0;
 	const u8 *dispatcher;
 	const u8 *dispatcherNoCheck;