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Small dispatcher optimizations, cleanup. Still no cube.

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This commit is contained in:
Henrik Rydgard 2013-01-09 00:12:38 +01:00
parent f5c94775b9
commit 81c6c4805d
3 changed files with 7 additions and 19 deletions
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22
Core/MIPS/ARM/ArmAsm.cpp
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@ -100,7 +100,7 @@ void ArmAsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
// R13 cannot be used as it's the stack pointer.
ARMABI_MOVI2R(R11, (u32)Memory::base);
ARMABI_MOVI2R(R10, (u32)mips);
ARMABI_MOVI2R(R7, (u32)jit->GetBlockCache()->GetCodePointers());
ARMABI_MOVI2R(R9, (u32)jit->GetBlockCache()->GetCodePointers());
outerLoop = GetCodePtr();
QuickCallFunction(R0, (void *)&CoreTiming::Advance);
@ -131,31 +131,19 @@ void ArmAsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
// MOV(R0, R13);
// QuickCallFunction(R1, (void *)&ShowPC);
ARMABI_MOVI2R(R7, (u32)jit->GetBlockCache()->GetCodePointers());
ARMABI_MOVI2R(R11, (u32)Memory::base);
ARMABI_MOVI2R(R10, (u32)mips);
LDR(R0, R10, offsetof(MIPSState, pc));
ARMABI_MOVI2R(R1, Memory::MEMVIEW32_MASK); // can be done with single MOVN instruction
AND(R0, R0, R1);
BIC(R0, R0, Operand2(0xC0, 4)); // &= 0x3FFFFFFF
ADD(R0, R0, R11); // TODO: Optimize (can merge with next instr)
LDR(R0, R0);
AND(R1, R0, Operand2(0xFC, 4)); // rotation is to the right, in 2-bit increments.
BIC(R0, R0, Operand2(0xFC, 4));
CMP(R1, Operand2(MIPS_EMUHACK_OPCODE >> 24, 4));
FixupBranch notfound = B_CC(CC_NEQ); // TODO : No need for a branch really, can use CCs.
SetCC(CC_EQ);
// IDEA - we have 24 bits, why not just use offsets from base of code?
if (enableDebug)
{
//ADD(32, M(&mips->debugCount), Imm8(1));
}
// grab from list and jump to it
ADD(R0, R7, Operand2(2, ST_LSL, R0));
ADD(R0, R9, Operand2(2, ST_LSL, R0));
LDR(R0, R0);
B(R0);
SetJumpTarget(notfound);
SetCC(CC_AL);
//Ok, no block, let's jit
ARMABI_CallFunction((void *)&Jit);

2
Core/MIPS/ARM/ArmCompALU.cpp
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@ -124,11 +124,11 @@ namespace MIPSComp
gpr.UnlockAll();
break;
*/
case 15: //R(rt) = uimm << 16; break; //lui
gpr.SetImm(rt, uimm << 16);
break;
*/
default:
Comp_Generic(op);

2
Core/MIPS/ARM/ArmRegCache.cpp
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@ -50,7 +50,7 @@ static const ARMReg *GetMIPSAllocationOrder(int &count) {
// R9 and upwards are reserved for jit basics.
// Six allocated registers should be enough...
static const ARMReg allocationOrder[] = {
R2, R3, R4, R5, R6 //, R7
R2, R3, R4, R5, R6, R7
};
count = sizeof(allocationOrder) / sizeof(const int);
return allocationOrder;