From 8327cd0f8e921cf14970234f5a6e59c885382e27 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Fri, 16 Aug 2013 02:02:56 -0700 Subject: [PATCH] Clean up some inconsistency in jit branches on arm. --- Core/MIPS/ARM/ArmCompBranch.cpp | 46 ++++++++++++++++----------------- Core/MIPS/ARM/ArmJit.cpp | 1 + Core/MIPS/ARM/ArmJit.h | 1 + Core/MIPS/x86/CompBranch.cpp | 2 +- 4 files changed, 26 insertions(+), 24 deletions(-) diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp index ba9c126de..69e625228 100644 --- a/Core/MIPS/ARM/ArmCompBranch.cpp +++ b/Core/MIPS/ARM/ArmCompBranch.cpp @@ -39,6 +39,8 @@ #define _FD ((op>>6 ) & 0x1F) #define _POS ((op>>6 ) & 0x1F) #define _SIZE ((op>>11 ) & 0x1F) +#define _IMM16 (signed short)(op&0xFFFF) +#define _IMM26 (op & 0x03FFFFFF) #define LOOPOPTIMIZATION 0 @@ -57,7 +59,7 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely) ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } - int offset = (signed short)(op&0xFFFF)<<2; + int offset = _IMM16 << 2; int rt = _RT; int rs = _RS; u32 targetAddr = js.compilerPC + offset + 4; @@ -101,11 +103,11 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely) } // Take the branch - WriteExit(targetAddr, 0); + WriteExit(targetAddr, js.nextExit++); SetJumpTarget(ptr); // Not taken - WriteExit(js.compilerPC+8, 1); + WriteExit(js.compilerPC+8, js.nextExit++); js.compiling = false; } @@ -117,7 +119,7 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } - int offset = (signed short)(op&0xFFFF)<<2; + int offset = _IMM16 << 2; int rs = _RS; u32 targetAddr = js.compilerPC + offset + 4; @@ -153,11 +155,11 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely STR(R0, CTXREG, MIPS_REG_RA * 4); } - WriteExit(targetAddr, 0); + WriteExit(targetAddr, js.nextExit++); SetJumpTarget(ptr); // Not taken - WriteExit(js.compilerPC + 8, 1); + WriteExit(js.compilerPC + 8, js.nextExit++); js.compiling = false; } @@ -183,7 +185,6 @@ void Jit::Comp_RelBranch(u32 op) _dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled"); break; } - js.compiling = false; } void Jit::Comp_RelBranchRI(u32 op) @@ -202,7 +203,6 @@ void Jit::Comp_RelBranchRI(u32 op) _dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled"); break; } - js.compiling = false; } // If likely is set, discard the branch slot if NOT taken. @@ -212,7 +212,7 @@ void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely) ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } - int offset = (signed short)(op & 0xFFFF) << 2; + int offset = _IMM16 << 2; u32 targetAddr = js.compilerPC + offset + 4; u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4); @@ -221,8 +221,6 @@ void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely) if (!likely && delaySlotIsNice) CompileDelaySlot(DELAYSLOT_NICE); - FlushAll(); - LDR(R0, CTXREG, offsetof(MIPSState, fpcond)); TST(R0, Operand2(1, TYPE_IMM)); @@ -231,20 +229,23 @@ void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely) { if (!delaySlotIsNice) CompileDelaySlot(DELAYSLOT_SAFE_FLUSH); + else + FlushAll(); ptr = B_CC(cc); } else { + FlushAll(); ptr = B_CC(cc); CompileDelaySlot(DELAYSLOT_FLUSH); } // Take the branch - WriteExit(targetAddr, 0); + WriteExit(targetAddr, js.nextExit++); SetJumpTarget(ptr); // Not taken - WriteExit(js.compilerPC + 8, 1); + WriteExit(js.compilerPC + 8, js.nextExit++); js.compiling = false; } @@ -260,7 +261,6 @@ void Jit::Comp_FPUBranch(u32 op) _dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted"); break; } - js.compiling = false; } // If likely is set, discard the branch slot if NOT taken. @@ -270,7 +270,7 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely) ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } - int offset = (signed short)(op & 0xFFFF) << 2; + int offset = _IMM16 << 2; u32 targetAddr = js.compilerPC + offset + 4; u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4); @@ -286,8 +286,6 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely) if (delaySlotIsBranch && (delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1) ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target", js.compilerPC); - FlushAll(); - int imm3 = (op >> 18) & 7; MOVI2R(R0, (u32)&(mips_->vfpuCtrl[VFPU_CTRL_CC])); @@ -300,10 +298,13 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely) { if (!delaySlotIsNice && !delaySlotIsBranch) CompileDelaySlot(DELAYSLOT_SAFE_FLUSH); + else + FlushAll(); ptr = B_CC(cc); } else { + FlushAll(); ptr = B_CC(cc); if (!delaySlotIsBranch) CompileDelaySlot(DELAYSLOT_FLUSH); @@ -311,12 +312,12 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely) js.inDelaySlot = false; // Take the branch - WriteExit(targetAddr, 0); + WriteExit(targetAddr, js.nextExit++); SetJumpTarget(ptr); // Not taken u32 notTakenTarget = js.compilerPC + (delaySlotIsBranch ? 4 : 8); - WriteExit(notTakenTarget, 1); + WriteExit(notTakenTarget, js.nextExit++); js.compiling = false; } @@ -329,7 +330,6 @@ void Jit::Comp_VBranch(u32 op) case 2: BranchVFPUFlag(op, CC_NEQ, true); break; // bvfl case 3: BranchVFPUFlag(op, CC_EQ, true); break; // bvtl } - js.compiling = false; } void Jit::Comp_Jump(u32 op) @@ -338,7 +338,7 @@ void Jit::Comp_Jump(u32 op) ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } - u32 off = ((op & 0x03FFFFFF) << 2); + u32 off = _IMM26 << 2; u32 targetAddr = (js.compilerPC & 0xF0000000) | off; switch (op >> 26) @@ -346,7 +346,7 @@ void Jit::Comp_Jump(u32 op) case 2: //j CompileDelaySlot(DELAYSLOT_NICE); FlushAll(); - WriteExit(targetAddr, 0); + WriteExit(targetAddr, js.nextExit++); break; case 3: //jal @@ -354,7 +354,7 @@ void Jit::Comp_Jump(u32 op) MOVI2R(gpr.R(MIPS_REG_RA), js.compilerPC + 8); CompileDelaySlot(DELAYSLOT_NICE); FlushAll(); - WriteExit(targetAddr, 0); + WriteExit(targetAddr, js.nextExit++); break; default: diff --git a/Core/MIPS/ARM/ArmJit.cpp b/Core/MIPS/ARM/ArmJit.cpp index 32dc5375d..9ff285102 100644 --- a/Core/MIPS/ARM/ArmJit.cpp +++ b/Core/MIPS/ARM/ArmJit.cpp @@ -193,6 +193,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b) { js.cancel = false; js.blockStart = js.compilerPC = mips_->pc; + js.nextExit = 0; js.downcountAmount = 0; js.curBlock = b; js.compiling = true; diff --git a/Core/MIPS/ARM/ArmJit.h b/Core/MIPS/ARM/ArmJit.h index b35601588..73bca7f25 100644 --- a/Core/MIPS/ARM/ArmJit.h +++ b/Core/MIPS/ARM/ArmJit.h @@ -55,6 +55,7 @@ struct ArmJitState u32 compilerPC; u32 blockStart; + int nextExit; bool cancel; bool inDelaySlot; int downcountAmount; diff --git a/Core/MIPS/x86/CompBranch.cpp b/Core/MIPS/x86/CompBranch.cpp index 7f9052dbf..0669236ee 100644 --- a/Core/MIPS/x86/CompBranch.cpp +++ b/Core/MIPS/x86/CompBranch.cpp @@ -39,7 +39,7 @@ #define _POS ((op>>6 ) & 0x1F) #define _SIZE ((op>>11 ) & 0x1F) #define _IMM16 (signed short)(op&0xFFFF) -#define _IMM26 (op & 0x3FFFFFF) +#define _IMM26 (op & 0x03FFFFFF) #define LOOPOPTIMIZATION 0