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ARM64 emitter: Add FMLA/FMLS vector versions

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This commit is contained in:
Henrik Rydgård 2015-04-04 19:46:15 +02:00 committed by Henrik Rydgard
parent 065cd97dc2
commit 853d6ea34b
4 changed files with 15 additions and 2 deletions
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8
Common/Arm64Emitter.cpp
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@ -2822,6 +2822,10 @@ void ARM64FloatEmitter::FADD(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
EmitThreeSame(0, size >> 6, 0x1A, Rd, Rn, Rm);
}
void ARM64FloatEmitter::FMLA(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
EmitThreeSame(0, size >> 6, 0x19, Rd, Rn, Rm);
}
void ARM64FloatEmitter::FCVTL(u8 size, ARM64Reg Rd, ARM64Reg Rn, bool source_upper)
{
Emit2RegMisc(source_upper, 0, size >> 6, 0x17, Rd, Rn);
@ -2858,6 +2862,10 @@ void ARM64FloatEmitter::FSUB(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
EmitThreeSame(0, 2 | (size >> 6), 0x1A, Rd, Rn, Rm);
}
void ARM64FloatEmitter::FMLS(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
EmitThreeSame(0, 2 | (size >> 6), 0x19, Rd, Rn, Rm);
}
void ARM64FloatEmitter::NOT(ARM64Reg Rd, ARM64Reg Rn)
{
Emit2RegMisc(IsQuad(Rd), 1, 0, 5, Rd, Rn);

2
Common/Arm64Emitter.h
View File

@ -802,6 +802,8 @@ public:
void DUP(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index);
void FABS(u8 size, ARM64Reg Rd, ARM64Reg Rn);
void FADD(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void FMLA(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void FMLS(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
void FCVTL(u8 size, ARM64Reg Rd, ARM64Reg Rn, bool source_upper = false);
void FCVTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
void FCVTZS(u8 size, ARM64Reg Rd, ARM64Reg Rn);

2
Core/Util/DisArm64.cpp
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@ -458,7 +458,7 @@ static void FPandASIMD1(uint32_t w, uint64_t addr, Instruction *instr) {
"fmaxnmp", 0, "faddp", "fmul",
"fcmge", "facge", "fmaxp", "fdiv",
};
const char *opnames010[8] = {
const char *opnames010[8] = {
"fminm", "fmls", "fsub", 0,
0, 0, "fmin", "frsqrts",
};

5
unittest/TestArm64Emitter.cpp
View File

@ -39,7 +39,10 @@ bool TestArm64Emitter() {
ARM64XEmitter emitter((u8 *)code);
ARM64FloatEmitter fp(&emitter);
fp.FMLA(32, D1, D2, D3);
RET(CheckLast(emitter, "0e23cc41 fmla.32 d1, d2, d3"));
fp.FMLS(64, Q1, Q2, Q3);
RET(CheckLast(emitter, "4ee3cc41 fmls.64 q1, q2, q3"));
fp.FADD(32, Q1, Q13, Q21);
RET(CheckLast(emitter, "4e35d5a1 fadd.32 q1, q13, q21"));
fp.FMUL(32, D1, D13, D21);