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arm64: Fix imm wasting when STP doesn't work out.

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This commit is contained in:
Unknown W. Brackets 2015-07-04 07:08:27 -07:00
parent 7a7d8b6489
commit 8ea7f99072
2 changed files with 11 additions and 4 deletions
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11
Core/MIPS/ARM64/Arm64RegCache.cpp
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@ -448,15 +448,22 @@ void Arm64RegCache::FlushAll() {
// If either one doesn't have a reg yet, try flushing imms to scratch regs.
if (areg1 == INVALID_REG && IsImm(mreg1)) {
SetRegImm(SCRATCH1, GetImm(mreg1));
areg1 = SCRATCH1;
}
if (areg2 == INVALID_REG && IsImm(mreg2)) {
SetRegImm(SCRATCH2, GetImm(mreg2));
areg2 = SCRATCH2;
}
if (areg1 != INVALID_REG && areg2 != INVALID_REG) {
// Actually put the imms in place now that we know we can do the STP.
// We didn't do it before in case the other wouldn't work.
if (areg1 == SCRATCH1) {
SetRegImm(areg1, GetImm(mreg1));
}
if (areg2 == SCRATCH2) {
SetRegImm(areg2, GetImm(mreg2));
}
// We can use a paired store, awesome.
emit_->STP(INDEX_SIGNED, areg1, areg2, CTXREG, GetMipsRegOffset(mreg1));

4
unittest/TestArm64Emitter.cpp
View File

@ -48,9 +48,9 @@ bool TestArm64Emitter() {
fp.UCVTF(32, D3, D7, 15);
RET(CheckLast(emitter, "2f31e4e3 ucvtf d3.s, d7.s, #15"));
fp.LDP(INDEX_SIGNED, Q3, Q7, X3, 32);
fp.LDP(128, INDEX_SIGNED, Q3, Q7, X3, 32);
RET(CheckLast(emitter, "ad411c63 ldp q3, q7, [x3, #32]"));
fp.STP(INDEX_SIGNED, Q3, Q7, X3, 32);
fp.STP(128, INDEX_SIGNED, Q3, Q7, X3, 32);
RET(CheckLast(emitter, "ad011c63 stp q3, q7, [x3, #32]"));
fp.DUP(32, Q1, Q30, 3);