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minor cleanup: No point in having special functions for ReadFCR/WriteFCR, they're smaller than many other ops..

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This commit is contained in:
Henrik Rydgård 2014-10-11 15:57:08 +02:00
parent 36291c5af7
commit 91966824bb
3 changed files with 37 additions and 36 deletions
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25
Core/MIPS/MIPS.cpp
View File

@ -305,31 +305,6 @@ int MIPSState::RunLoopUntil(u64 globalTicks) {
return 1;
}
void MIPSState::WriteFCR(int reg, int value) {
if (reg == 31) {
fcr31 = value & 0x0181FFFF;
fpcond = (value >> 23) & 1;
} else {
WARN_LOG_REPORT(CPU, "WriteFCR: Unexpected reg %d (value %08x)", reg, value);
// MessageBox(0, "Invalid FCR","...",0);
}
DEBUG_LOG(CPU, "FCR%i written to, value %08x", reg, value);
}
u32 MIPSState::ReadFCR(int reg) {
DEBUG_LOG(CPU,"FCR%i read",reg);
if (reg == 31) {
fcr31 = (fcr31 & ~(1<<23)) | ((fpcond & 1)<<23);
return fcr31;
} else if (reg == 0) {
return FCR0_VALUE;
} else {
WARN_LOG_REPORT(CPU, "ReadFCR: Unexpected reg %d", reg);
// MessageBox(0, "Invalid FCR","...",0);
}
return 0;
}
void MIPSState::InvalidateICache(u32 address, int length) {
// Only really applies to jit.
if (MIPSComp::jit)

3
Core/MIPS/MIPS.h
View File

@ -178,9 +178,6 @@ public:
static const u32 FCR0_VALUE = 0x00003351;
void WriteFCR(int reg, int value);
u32 ReadFCR(int reg);
u8 VfpuWriteMask() const {
return (vfpuCtrl[VFPU_CTRL_DPREFIX] >> 8) & 0xF;
}

45
Core/MIPS/MIPSInt.cpp
View File

@ -527,12 +527,41 @@ namespace MIPSInt
int fs = _FS;
int rt = _RT;
switch((op>>21)&0x1f)
{
case 0: if (rt != 0) R(rt) = FI(fs); break; //mfc1
case 2: if (rt != 0) R(rt) = currentMIPS->ReadFCR(fs); break; //cfc1
case 4: FI(fs) = R(rt); break; //mtc1
case 6: currentMIPS->WriteFCR(fs, R(rt)); break; //ctc1
switch ((op>>21)&0x1f) {
case 0: //mfc1
if (rt != 0)
R(rt) = FI(fs);
break;
case 2: //cfc1
if (rt != 0) {
if (fs == 31) {
currentMIPS->fcr31 = (currentMIPS->fcr31 & ~(1<<23)) | ((currentMIPS->fpcond & 1)<<23);
R(rt) = currentMIPS->fcr31;
} else if (fs == 0) {
R(rt) = MIPSState::FCR0_VALUE;
} else {
WARN_LOG_REPORT(CPU, "ReadFCR: Unexpected reg %d", fs);
}
break;
}
case 4: //mtc1
FI(fs) = R(rt);
break;
case 6: //ctc1
{
u32 value = R(rt);
if (fs == 31) {
currentMIPS->fcr31 = value & 0x0181FFFF;
currentMIPS->fpcond = (value >> 23) & 1;
} else {
WARN_LOG_REPORT(CPU, "WriteFCR: Unexpected reg %d (value %08x)", fs, value);
}
DEBUG_LOG(CPU, "FCR%i written to, value %08x", fs, value);
break;
}
default:
_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
@ -818,14 +847,14 @@ namespace MIPSInt
static int reported = 0;
switch (op & 0x3F)
{
case 36:
case 36: // mfic
if (!reported) {
Reporting::ReportMessage("MFIC instruction hit (%08x) at %08x", op, currentMIPS->pc);
WARN_LOG(CPU,"MFIC Disable/Enable Interrupt CPU instruction");
reported = 1;
}
break;
case 38:
case 38: // mtic
if (!reported) {
Reporting::ReportMessage("MTIC instruction hit (%08x) at %08x", op, currentMIPS->pc);
WARN_LOG(CPU,"MTIC Disable/Enable Interrupt CPU instruction");