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Merge pull request #7200 from unknownbrackets/warnings

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Nix some warnings
This commit is contained in:
Henrik Rydgård 2014-12-20 19:23:34 +01:00
commit 9cbbe2d42a
4 changed files with 11 additions and 11 deletions
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1
Core/Config.cpp
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@ -1139,6 +1139,7 @@ bool Config::saveGameConfig()
KeyMap::SaveToIni(iniFile);
iniFile.Save(fullIniFilePath);
return true;
}
bool Config::loadGameConfig(const std::string &pGameId)

8
Core/HLE/sceMp4.cpp
View File

@ -82,12 +82,6 @@ static u32 sceMp4TrackSampleBufAvailableSize(u32 mp4, u32 unknown2)
return 0;
}
static u32 sceMp4CreatesceMp4GetNumberOfMetaData()
{
ERROR_LOG(ME, "UNIMPL sceMp4GetNumberOfMetaData()");
return 0;
}
static u32 sceMp4Delete()
{
ERROR_LOG(ME, "UNIMPL sceMp4Delete()");
@ -239,7 +233,7 @@ static u32 sceAacInit(u32 id)
delete aac;
return ERROR_AAC_INVALID_ADDRESS;
}
if (aac->startPos < 0 || aac->startPos > aac->endPos) {
if (aac->startPos > aac->endPos) {
ERROR_LOG(ME, "sceAacInit() AAC INVALID startPos %lli endPos %lli", aac->startPos, aac->endPos);
delete aac;
return ERROR_AAC_INVALID_PARAMETER;

6
Core/MIPS/MIPSIntVFPU.cpp
View File

@ -701,8 +701,7 @@ namespace MIPSInt
d[2] = ExpandHalf(s[1] & 0xFFFF);
d[3] = ExpandHalf(s[1] >> 16);
break;
case V_Triple:
case V_Quad:
default:
_dbg_assert_msg_(CPU, 0, "Trying to interpret Int_Vh2f instruction that can't be interpreted");
break;
}
@ -733,8 +732,7 @@ namespace MIPSInt
d[0] = ShrinkToHalf(s[0]) | ((u32)ShrinkToHalf(s[1]) << 16);
d[1] = ShrinkToHalf(s[2]) | ((u32)ShrinkToHalf(s[3]) << 16);
break;
case V_Single:
case V_Triple:
default:
_dbg_assert_msg_(CPU, 0, "Trying to interpret Int_Vf2h instruction that can't be interpreted");
break;
}

7
Core/MIPS/x86/CompVFPU.cpp
View File

@ -659,6 +659,9 @@ void Jit::Comp_VDot(MIPSOpcode op) {
ADDSS(XMM0, R(XMM1));
MOVAPS(fpr.VSX(dregs), R(XMM0));
}
break;
default:
DISABLE;
}
ApplyPrefixD(dregs, V_Single);
fpr.ReleaseSpillLocks();
@ -3081,6 +3084,8 @@ void Jit::Comp_Vhoriz(MIPSOpcode op) {
DPPS(XMM0, M(&oneOneOneOne), 0xF1);
MOVAPS(fpr.VSX(dregs), R(XMM0));
break;
default:
DISABLE;
}
} else {
switch (sz) {
@ -3109,6 +3114,8 @@ void Jit::Comp_Vhoriz(MIPSOpcode op) {
ADDPS(XMM0, R(XMM1));
MOVAPS(fpr.VSX(dregs), R(XMM0));
break;
default:
DISABLE;
}
}
if (((op >> 16) & 31) == 7) { // vavg