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Some comment fixes and cleanup.

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Not much point warning for those MIPS instructions - if games use them,
they use them carefully because games can't catch that exception anyway.
This commit is contained in:
Henrik Rydgård 2018-04-12 12:00:19 +02:00
parent 31ae11ecc8
commit a3ed87bca5
2 changed files with 6 additions and 19 deletions
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16
Core/MIPS/MIPSInt.cpp
View File

@ -375,19 +375,9 @@ namespace MIPSInt
{
case 10: if (R(rt) == 0) R(rd) = R(rs); break; //movz
case 11: if (R(rt) != 0) R(rd) = R(rs); break; //movn
case 32:
if (!has_warned) {
ERROR_LOG(CPU,"WARNING : exception-causing add at %08x", PC);
has_warned = true;
}
R(rd) = R(rs) + R(rt); break; //add
case 32: R(rd) = R(rs) + R(rt); break; //add (exception on overflow)
case 33: R(rd) = R(rs) + R(rt); break; //addu
case 34:
if (!has_warned) {
ERROR_LOG(CPU,"WARNING : exception-causing sub at %08x", PC);
has_warned = true;
}
R(rd) = R(rs) - R(rt); break; //sub
case 34: R(rd) = R(rs) - R(rt); break; //sub (exception on overflow)
case 35: R(rd) = R(rs) - R(rt); break; //subu
case 36: R(rd) = R(rs) & R(rt); break; //and
case 37: R(rd) = R(rs) | R(rt); break; //or
@ -398,7 +388,7 @@ namespace MIPSInt
case 44: R(rd) = ((s32)R(rs) > (s32)R(rt)) ? R(rs) : R(rt); break; //max
case 45: R(rd) = ((s32)R(rs) < (s32)R(rt)) ? R(rs) : R(rt); break;//min
default:
_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
_dbg_assert_msg_(CPU, 0, "Unknown MIPS instruction %08x", op.encoding);
break;
}
PC += 4;

9
GPU/Vulkan/DrawEngineVulkan.cpp
View File

@ -1003,14 +1003,11 @@ DrawEngineVulkan::TessellationDataTransferVulkan::TessellationDataTransferVulkan
DrawEngineVulkan::TessellationDataTransferVulkan::~TessellationDataTransferVulkan() {
}
// TODO: Consolidate the three textures into one, with height 3.
// This can be done for all the backends.
// TODO: Actually, even better, avoid the usage of textures altogether and just use shader storage buffers from the current pushbuffer.
void DrawEngineVulkan::TessellationDataTransferVulkan::PrepareBuffers(float *&pos, float *&tex, float *&col, int &posStride, int &texStride, int &colStride, int size, bool hasColor, bool hasTexCoords) {
colStride = 4;
// TODO: This SHOULD work without padding but I can't get it to work on nvidia, so had
// to expand to vec4. Driver bug?
// SSBOs that are not simply float1 or float2 need to be padded up to a float4 size. vec3 members
// also need to be 16-byte aligned, hence the padding.
struct TessData {
float pos[3]; float pad1;
float uv[2]; float pad2[2];
@ -1030,5 +1027,5 @@ void DrawEngineVulkan::TessellationDataTransferVulkan::PrepareBuffers(float *&po
}
void DrawEngineVulkan::TessellationDataTransferVulkan::SendDataToShader(const float *pos, const float *tex, const float *col, int size, bool hasColor, bool hasTexCoords) {
// Nothing to do here!
// Nothing to do here! The caller will write directly to the pushbuffer through the pointers it got through PrepareBuffers.
}