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Prefix prep

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This commit is contained in:
Henrik Rydgard 2016-05-10 23:14:26 +02:00
parent db1d1ff9fd
commit b3dd36982f
4 changed files with 21 additions and 17 deletions
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26
Core/MIPS/IR/IRCompVFPU.cpp
View File

@ -152,17 +152,21 @@ namespace MIPSComp {
int n = GetNumVectorElements(sz);
for (int i = 0; i < n; i++) {
// Hopefully this is rare, we'll just write it into a reg we drop.
//if (js.VfpuWriteMask(i))
// regs[i] = fpr.GetTempV();
if (js.VfpuWriteMask(i))
regs[i] = fpr.GetTempV();
}
}
inline int GetDSat(int prefix, int i) {
return (prefix >> (i * 2)) & 3;
}
// "D" prefix is really a post process. No need to allocate a temporary register.
void IRFrontend::ApplyPrefixD(const u8 *vregs, VectorSize sz) {
_assert_(js.prefixDFlag & JitState::PREFIX_KNOWN);
if (!js.prefixD)
return;
/*
int n = GetNumVectorElements(sz);
for (int i = 0; i < n; i++) {
if (js.VfpuWriteMask(i))
@ -171,23 +175,11 @@ namespace MIPSComp {
int sat = (js.prefixD >> (i * 2)) & 3;
if (sat == 1) {
// clamped = x < 0 ? (x > 1 ? 1 : x) : x [0, 1]
fpr.MapRegV(vregs[i], MAP_DIRTY);
fp.MOVI2F(S0, 0.0f, SCRATCH1);
fp.MOVI2F(S1, 1.0f, SCRATCH1);
fp.FMIN(fpr.V(vregs[i]), fpr.V(vregs[i]), S1);
fp.FMAX(fpr.V(vregs[i]), fpr.V(vregs[i]), S0);
ir.Write(IROp::FSat0_1, vfpuBase + voffset[vregs[i]], vfpuBase + voffset[vregs[i]]);
} else if (sat == 3) {
// clamped = x < -1 ? (x > 1 ? 1 : x) : x [-1, 1]
fpr.MapRegV(vregs[i], MAP_DIRTY);
fp.MOVI2F(S0, -1.0f, SCRATCH1);
fp.MOVI2F(S1, 1.0f, SCRATCH1);
fp.FMIN(fpr.V(vregs[i]), fpr.V(vregs[i]), S1);
fp.FMAX(fpr.V(vregs[i]), fpr.V(vregs[i]), S0);
ir.Write(IROp::FSatMinus1_1, vfpuBase + voffset[vregs[i]], vfpuBase + voffset[vregs[i]]);
}
}
*/
}
void IRFrontend::Comp_SV(MIPSOpcode op) {

2
Core/MIPS/IR/IRInst.cpp
View File

@ -78,6 +78,8 @@ static const IRMeta irMeta[] = {
{ IROp::FFloor, "FFloor", "FF" },
{ IROp::FCvtWS, "FCvtWS", "FF" },
{ IROp::FCvtSW, "FCvtSW", "FF" },
{ IROp::FSat0_1, "FSat(0 - 1)", "FF" },
{ IROp::FSatMinus1_1, "FSat(-1 - 1)", "FF" },
{ IROp::FMovFromGPR, "FMovFromGPR", "FG" },
{ IROp::FMovToGPR, "FMovToGPR", "GF" },
{ IROp::InitVec4, "InitVec4", "Fv"},

3
Core/MIPS/IR/IRInst.h
View File

@ -120,6 +120,9 @@ enum class IROp : u8 {
FMovFromGPR,
FMovToGPR,
FSat0_1,
FSatMinus1_1,
FpCondToReg,
VfpuCtrlToReg,

7
Core/MIPS/IR/IRInterpreter.cpp
View File

@ -303,6 +303,13 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
case IROp::FNeg:
mips->f[inst->dest] = -mips->f[inst->src1];
break;
case IROp::FSat0_1:
mips->f[inst->dest] = clamp_value(mips->f[inst->src1], 0.0f, 1.0f);
break;
case IROp::FSatMinus1_1:
mips->f[inst->dest] = clamp_value(mips->f[inst->src1], -1.0f, 1.0f);
break;
case IROp::FpCondToReg:
mips->r[inst->dest] = mips->fpcond;
break;