libretro/ppsspp
1
0
Fork 0
mirror of https://github.com/libretro/ppsspp.git synced 2024-11-30 20:01:00 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

x86jit: Improve cvt.w.s when fd is loaded or fs.

Browse Source 
We have no need to store it.
This commit is contained in:
Unknown W. Brackets 2014-11-08 16:37:30 -08:00
parent 76469debfb
commit bed0d0b059
2 changed files with 35 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Core/MIPS/x86/CompFPU.cpp
View File

@ -264,7 +264,6 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
case 13: //FsI(fd) = F(fs)>=0 ? (int)floorf(F(fs)) : (int)ceilf(F(fs)); break;//trunc.w.s
{
fpr.SpillLock(fs, fd);
fpr.StoreFromRegister(fd);
CVTTSS2SI(EAX, fpr.R(fs));
// Did we get an indefinite integer value?
@ -280,11 +279,13 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
XOR(32, R(EAX), Imm32(0x7fffffff));
SetJumpTarget(skip);
fpr.DiscardR(fd);
MOV(32, fpr.R(fd), R(EAX));
}
break;
case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fs == fd, true);
if (fpr.R(fs).IsSimpleReg()) {
CVTDQ2PS(fpr.RX(fd), fpr.R(fs));
@ -297,8 +298,7 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
{
fpr.SpillLock(fs, fd);
fpr.StoreFromRegister(fd);
fpr.SpillLock(fs);
CVTSS2SI(EAX, fpr.R(fs));
// Did we get an indefinite integer value?
@ -314,6 +314,7 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
XOR(32, R(EAX), Imm32(0x7fffffff));
SetJumpTarget(skip);
fpr.DiscardR(fd);
MOV(32, fpr.R(fd), R(EAX));
}
break;

37
unittest/JitHarness.cpp
View File

@ -41,7 +41,9 @@ InputState input_state;
#endif
void UnitTestTerminator() {
// Bails out of jit so we can time things.
coreState = CORE_POWERDOWN;
hleSkipDeadbeef();
}
HLEFunction UnitTestFakeSyscalls[] = {
@ -102,7 +104,21 @@ bool TestJit() {
u32 *p = (u32 *)Memory::GetPointer(currentMIPS->pc);
// TODO: Smarter way of seeding in the code sequence.
static const char *lines[] = {
"abs.s f1, f1",
"cvt.w.s f1, f1",
"cvt.w.s f3, f1",
"cvt.w.s f0, f2",
"cvt.w.s f5, f1",
"cvt.w.s f6, f5",
};
bool compileSuccess = true;
u32 addr = currentMIPS->pc;
DebugInterface *dbg = currentDebugMIPS;
for (int i = 0; i < 100; ++i) {
/*
// VFPU ops aren't supported by MIPSAsm yet.
*p++ = 0xD03C0000 | (1 << 7) | (1 << 15) | (7 << 8);
*p++ = 0xD03C0000 | (1 << 7) | (1 << 15);
*p++ = 0xD03C0000 | (1 << 7) | (1 << 15) | (7 << 8);
@ -110,18 +126,27 @@ bool TestJit() {
*p++ = 0xD03C0000 | (1 << 7) | (1 << 15) | (7 << 8);
*p++ = 0xD03C0000 | (1 << 7) | (1 << 15) | (7 << 8);
*p++ = 0xD03C0000 | (1 << 7) | (1 << 15) | (7 << 8);
*/
for (size_t j = 0; j < ARRAY_SIZE(lines); ++j) {
if (!MIPSAsm::MipsAssembleOpcode(lines[j], currentDebugMIPS, addr, *p++)) {
printf("ERROR: %s\n", MIPSAsm::GetAssembleError());
compileSuccess = false;
}
addr += 4;
}
}
*p++ = MIPS_MAKE_SYSCALL("UnitTestFakeSyscalls", "UnitTestTerminator");
*p++ = MIPS_MAKE_BREAK(1);
double interp_speed = ExecCPUTest();
double jit_speed, interp_speed;
if (compileSuccess) {
interp_speed = ExecCPUTest();
mipsr4k.UpdateCore(CPU_JIT);
jit_speed = ExecCPUTest();
mipsr4k.UpdateCore(CPU_JIT);
double jit_speed = ExecCPUTest();
printf("Jit was %fx faster than interp.\n", jit_speed / interp_speed);
printf("Jit was %fx faster than interp.\n", jit_speed / interp_speed);
}
DestroyJitHarness();