Endian and PPC support

Core/CoreParameter.h

@@ -29,6 +29,7 @@ enum GPUCore {
 	GPU_NULL,
 	GPU_GLES,
 	GPU_SOFTWARE,
+	GPU_DIRECTX9,
 };
 
 struct CoreParameter

Core/HLE/sceKernelModule.cpp

@@ -659,7 +659,8 @@ Module *__KernelLoadELFFromPtr(const u8 *ptr, u32 loadAddress, std::string *erro
 
 				u32_le *varRef = (u32_le *)Memory::GetPointer(varRefsPtr);
 				for (; *varRef != 0; ++varRef) {
-					ImportVarSymbol(modulename, nid, (*varRef & 0x03FFFFFF) << 2, *varRef >> 26);
+					u8 type = (u8)(u32)((*varRef) >> 26);
+					ImportVarSymbol(modulename, nid, (*varRef & 0x03FFFFFF) << 2, type);
 				}
 			}
 		} else if (entry->numVars > 0) {

Core/MIPS/JitCommon/JitCommon.h

@@ -19,7 +19,9 @@
 
 #include "Common/Common.h"
 
-#if defined(ARM)
+#if defined(PPC) 
+#include "../PPC/PpcJit.h"
+#elif defined(ARM)
 #include "../ARM/ArmJit.h"
 #else
 #include "../x86/Jit.h"

Core/MIPS/PPC/PpcJit.cpp

@@ -0,0 +1,70 @@
+#include "PpcJit.h"
+
+namespace MIPSComp
+{
+	Jit * jit=NULL;
+
+	void Jit::Comp_Generic(u32 op) {
+
+	}
+	
+	void Jit::EatInstruction(u32 op){}
+	void Jit::Comp_RunBlock(u32 op){}
+	void Jit::Comp_ITypeMem(u32 op){}
+
+	void Jit::Comp_RelBranch(u32 op){}
+	void Jit::Comp_RelBranchRI(u32 op){}
+	void Jit::Comp_FPUBranch(u32 op){}
+	void Jit::Comp_FPULS(u32 op){}
+	void Jit::Comp_FPUComp(u32 op){}
+	void Jit::Comp_Jump(u32 op){}
+	void Jit::Comp_JumpReg(u32 op){}
+	void Jit::Comp_Syscall(u32 op){}
+	void Jit::Comp_Break(u32 op){}
+
+	void Jit::Comp_IType(u32 op){}
+	void Jit::Comp_RType2(u32 op){}
+	void Jit::Comp_RType3(u32 op){}
+	void Jit::Comp_ShiftType(u32 op){}
+	void Jit::Comp_Allegrex(u32 op){}
+	void Jit::Comp_Allegrex2(u32 op){}
+	void Jit::Comp_VBranch(u32 op){}
+	void Jit::Comp_MulDivType(u32 op){}
+	void Jit::Comp_Special3(u32 op){}
+
+	void Jit::Comp_FPU3op(u32 op){}
+	void Jit::Comp_FPU2op(u32 op){}
+	void Jit::Comp_mxc1(u32 op){}
+
+	void Jit::Comp_DoNothing(u32 op){}
+
+	void Jit::Comp_SV(u32 op){}
+	void Jit::Comp_SVQ(u32 op){}
+	void Jit::Comp_VPFX(u32 op){}
+	void Jit::Comp_VVectorInit(u32 op){}
+	void Jit::Comp_VMatrixInit(u32 op){}
+	void Jit::Comp_VDot(u32 op){}
+	void Jit::Comp_VecDo3(u32 op){}
+	void Jit::Comp_VV2Op(u32 op){}
+	void Jit::Comp_Mftv(u32 op){}
+	void Jit::Comp_Vmtvc(u32 op){}
+	void Jit::Comp_Vmmov(u32 op){}
+	void Jit::Comp_VScl(u32 op){}
+	void Jit::Comp_Vmmul(u32 op){}
+	void Jit::Comp_Vmscl(u32 op){}
+	void Jit::Comp_Vtfm(u32 op){}
+	void Jit::Comp_VHdp(u32 op){}
+	void Jit::Comp_VCrs(u32 op){}
+	void Jit::Comp_VDet(u32 op){}
+	void Jit::Comp_Vi2x(u32 op){}
+	void Jit::Comp_Vx2i(u32 op){}
+	void Jit::Comp_Vf2i(u32 op){}
+	void Jit::Comp_Vi2f(u32 op){}
+	void Jit::Comp_Vcst(u32 op){}
+	void Jit::Comp_Vhoriz(u32 op){}
+	void Jit::Comp_VRot(u32 op){}
+	void Jit::Comp_VIdt(u32 op){}
+
+	void Jit::ClearCache(){}
+	void Jit::ClearCacheAt(u32 em_address){}
+}

Core/MIPS/PPC/PpcJit.h

@@ -0,0 +1,102 @@
+// Copyright (c) 2012- PPSSPP Project.
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, version 2.0 or later versions.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License 2.0 for more details.
+
+// A copy of the GPL 2.0 should have been included with the program.
+// If not, see http://www.gnu.org/licenses/
+
+// Official git repository and contact information can be found at
+// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
+
+#pragma once
+
+#include "../../../Globals.h"
+
+namespace MIPSComp
+{
+
+class Jit
+{
+public:
+	// Compiled ops should ignore delay slots
+	// the compiler will take care of them by itself
+	// OR NOT
+	void Comp_Generic(u32 op);
+	
+	void EatInstruction(u32 op);
+	void Comp_RunBlock(u32 op);
+	
+	// TODO: Eat VFPU prefixes here.
+	void EatPrefix() { }
+
+	// Ops
+	void Comp_ITypeMem(u32 op);
+
+	void Comp_RelBranch(u32 op);
+	void Comp_RelBranchRI(u32 op);
+	void Comp_FPUBranch(u32 op);
+	void Comp_FPULS(u32 op);
+	void Comp_FPUComp(u32 op);
+	void Comp_Jump(u32 op);
+	void Comp_JumpReg(u32 op);
+	void Comp_Syscall(u32 op);
+	void Comp_Break(u32 op);
+
+	void Comp_IType(u32 op);
+	void Comp_RType2(u32 op);
+	void Comp_RType3(u32 op);
+	void Comp_ShiftType(u32 op);
+	void Comp_Allegrex(u32 op);
+	void Comp_Allegrex2(u32 op);
+	void Comp_VBranch(u32 op);
+	void Comp_MulDivType(u32 op);
+	void Comp_Special3(u32 op);
+
+	void Comp_FPU3op(u32 op);
+	void Comp_FPU2op(u32 op);
+	void Comp_mxc1(u32 op);
+
+	void Comp_DoNothing(u32 op);
+
+	void Comp_SV(u32 op);
+	void Comp_SVQ(u32 op);
+	void Comp_VPFX(u32 op);
+	void Comp_VVectorInit(u32 op);	
+	void Comp_VMatrixInit(u32 op);
+	void Comp_VDot(u32 op);
+	void Comp_VecDo3(u32 op);
+	void Comp_VV2Op(u32 op);
+	void Comp_Mftv(u32 op);
+	void Comp_Vmtvc(u32 op);
+	void Comp_Vmmov(u32 op);
+	void Comp_VScl(u32 op);
+	void Comp_Vmmul(u32 op);
+	void Comp_Vmscl(u32 op);
+	void Comp_Vtfm(u32 op);
+	void Comp_VHdp(u32 op);
+	void Comp_VCrs(u32 op);
+	void Comp_VDet(u32 op);
+	void Comp_Vi2x(u32 op);
+	void Comp_Vx2i(u32 op);
+	void Comp_Vf2i(u32 op);
+	void Comp_Vi2f(u32 op);
+	void Comp_Vcst(u32 op);
+	void Comp_Vhoriz(u32 op);	
+	void Comp_VRot(u32 op);
+	void Comp_VIdt(u32 op);
+
+	void ClearCache();
+	void ClearCacheAt(u32 em_address);
+};
+
+typedef void (Jit::*MIPSCompileFunc)(u32 opcode);
+
+}	// namespace MIPSComp
+

Core/MemMap.cpp

@@ -124,6 +124,7 @@ void Clear()
 
 u32 Read_Instruction(u32 address)
 {
+#ifndef NO_JIT
 	u32 inst = Read_U32(address);	
 	if (MIPS_IS_EMUHACK(inst) && MIPSComp::jit)
 	{
@@ -137,6 +138,9 @@ u32 Read_Instruction(u32 address)
 	} else {
 		return inst;
 	}
+#else
+	return Read_U32(address);
+#endif
 }
 
 u32 Read_Opcode_JIT(u32 address)

Core/MemMap.h

@@ -136,23 +136,23 @@ void WriteUnchecked_U32(const u32 _Data, const u32 _Address);
 #else
 
 inline u32 ReadUnchecked_U32(const u32 address) {
-#if defined(_M_IX86) || defined(_M_ARM32)
-  return (*(u32 *)(base + (address & MEMVIEW32_MASK)));
+#if defined(_M_IX86) || defined(_M_ARM32) || defined (_XBOX)
+  return LE_32(*(u32 *)(base + (address & MEMVIEW32_MASK)));
 #else
-  return (*(u32 *)(base + address));
+  return LE_32(*(u32 *)(base + address));
 #endif
 }
 
 inline u16 ReadUnchecked_U16(const u32 address) {
-#if defined(_M_IX86) || defined(_M_ARM32)
-	return (*(u16 *)(base + (address & MEMVIEW32_MASK)));
+#if defined(_M_IX86) || defined(_M_ARM32) || defined (_XBOX)
+	return LE_16(*(u16 *)(base + (address & MEMVIEW32_MASK)));
 #else
-	return (*(u16 *)(base + address));
+	return LE_16(*(u16 *)(base + address));
 #endif
 }
 
 inline u8 ReadUnchecked_U8(const u32 address) {
-#if defined(_M_IX86) || defined(_M_ARM32)
+#if defined(_M_IX86) || defined(_M_ARM32) || defined (_XBOX)
 	return (*(u8 *)(base + (address & MEMVIEW32_MASK))); 
 #else
 	return (*(u8 *)(base + address));
@@ -160,23 +160,23 @@ inline u8 ReadUnchecked_U8(const u32 address) {
 }
 
 inline void WriteUnchecked_U32(u32 data, u32 address) {
-#if defined(_M_IX86) || defined(_M_ARM32)
-	(*(u32 *)(base + (address & MEMVIEW32_MASK))) = data;
+#if defined(_M_IX86) || defined(_M_ARM32) || defined (_XBOX)
+	(*(u32 *)(base + (address & MEMVIEW32_MASK))) = LE_32(data);
 #else
-	(*(u32 *)(base + address)) = data;
+	(*(u32 *)(base + address)) = LE_32(data);
 #endif
 }
 
 inline void WriteUnchecked_U16(u16 data, u32 address) {
-#if defined(_M_IX86) || defined(_M_ARM32)
-	(*(u16 *)(base + (address & MEMVIEW32_MASK))) = data;
+#if defined(_M_IX86) || defined(_M_ARM32) || defined (_XBOX)
+	(*(u16 *)(base + (address & MEMVIEW32_MASK))) = LE_16(data);
 #else
-	(*(u16 *)(base + address)) = data;
+	(*(u16 *)(base + address)) = LE_16(data);
 #endif
 }
 
 inline void WriteUnchecked_U8(u8 data, u32 address) {
-#if defined(_M_IX86) || defined(_M_ARM32)
+#if defined(_M_IX86) || defined(_M_ARM32) || defined (_XBOX)
 	(*(u8 *)(base + (address & MEMVIEW32_MASK))) = data;
 #else
 	(*(u8 *)(base + address)) = data;

Core/MemMapFunctions.cpp

@@ -158,21 +158,21 @@ u16 Read_U16(const u32 _Address)
 {
 	u16 _var = 0;
 	ReadFromHardware<u16>(_var, _Address);
-	return (u16)_var;
+	return (u16)LE_16(_var);
 }
 
 u32 Read_U32(const u32 _Address)
 {
 	u32 _var = 0;	
 	ReadFromHardware<u32>(_var, _Address);
-	return _var;
+	return LE_32(_var);
 }
 
 u64 Read_U64(const u32 _Address)
 {
 	u64 _var = 0;
 	ReadFromHardware<u64>(_var, _Address);
-	return _var;
+	return LE_64(_var);
 }
 
 u32 Read_U8_ZX(const u32 _Address)
@@ -193,17 +193,17 @@ void Write_U8(const u8 _Data, const u32 _Address)
 
 void Write_U16(const u16 _Data, const u32 _Address)
 {
-	WriteToHardware<u16>(_Address, _Data);
+	WriteToHardware<u16>(_Address, LE_16(_Data));
 }
 
 void Write_U32(const u32 _Data, const u32 _Address)
 {	
-	WriteToHardware<u32>(_Address, _Data);
+	WriteToHardware<u32>(_Address, LE_32(_Data));
 }
 
 void Write_U64(const u64 _Data, const u32 _Address)
 {
-	WriteToHardware<u64>(_Address, _Data);
+	WriteToHardware<u64>(_Address, LE_64(_Data));
 }
 
 #ifdef SAFE_MEMORY
@@ -219,14 +219,14 @@ u16 ReadUnchecked_U16(const u32 _Address)
 {
 	u16 _var = 0;
 	ReadFromHardware<u16>(_var, _Address);
-	return _var;
+	return LE_16(_var);
 }
 
 u32 ReadUnchecked_U32(const u32 _Address)
 {
 	u32 _var = 0;
 	ReadFromHardware<u32>(_var, _Address);
-	return _var;
+	return LE_32(_var);
 }
 
 void WriteUnchecked_U8(const u8 _iValue, const u32 _Address)
@@ -236,12 +236,12 @@ void WriteUnchecked_U8(const u8 _iValue, const u32 _Address)
 
 void WriteUnchecked_U16(const u16 _iValue, const u32 _Address)
 {
-	WriteToHardware<u16>(_Address, _iValue);
+	WriteToHardware<u16>(_Address, LE_16(_iValue));
 }
 
 void WriteUnchecked_U32(const u32 _iValue, const u32 _Address)
 {
-	WriteToHardware<u32>(_Address, _iValue);
+	WriteToHardware<u32>(_Address, LE_32(_iValue));
 }
 
 #endif