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armjit: Fix divu when divisor is a constant 1.

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Fixes #4539 and #4520.
This commit is contained in:
Unknown W. Brackets 2013-11-19 13:24:15 -08:00
parent bd3a03ad1d
commit c50ab6d6aa
2 changed files with 21 additions and 5 deletions
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20
Common/ArmEmitter.cpp
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@ -735,12 +735,24 @@ void ARMXEmitter::LSL (ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedData
void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(0, true, dest, src, op2);}
void ARMXEmitter::LSL (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, false, dest, src, op2);}
void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, true, dest, src, op2);}
void ARMXEmitter::LSR (ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(2, false, dest, src, op2);}
void ARMXEmitter::LSRS(ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(2, true, dest, src, op2);}
void ARMXEmitter::LSR (ARMReg dest, ARMReg src, Operand2 op2) {
_assert_msg_(JIT, op2.GetType() != TYPE_IMM || op2.Imm5() != 0, "LSR must have a non-zero shift (use LSL.)");
WriteShiftedDataOp(2, false, dest, src, op2);
}
void ARMXEmitter::LSRS(ARMReg dest, ARMReg src, Operand2 op2) {
_assert_msg_(JIT, op2.GetType() != TYPE_IMM || op2.Imm5() != 0, "LSRS must have a non-zero shift (use LSLS.)");
WriteShiftedDataOp(2, true, dest, src, op2);
}
void ARMXEmitter::LSR (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(3, false, dest, src, op2);}
void ARMXEmitter::LSRS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(3, true, dest, src, op2);}
void ARMXEmitter::ASR (ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(4, false, dest, src, op2);}
void ARMXEmitter::ASRS(ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(4, true, dest, src, op2);}
void ARMXEmitter::ASR (ARMReg dest, ARMReg src, Operand2 op2) {
_assert_msg_(JIT, op2.GetType() != TYPE_IMM || op2.Imm5() != 0, "ASR must have a non-zero shift (use LSL.)");
WriteShiftedDataOp(4, false, dest, src, op2);
}
void ARMXEmitter::ASRS(ARMReg dest, ARMReg src, Operand2 op2) {
_assert_msg_(JIT, op2.GetType() != TYPE_IMM || op2.Imm5() != 0, "ASRS must have a non-zero shift (use LSLS.)");
WriteShiftedDataOp(4, true, dest, src, op2);
}
void ARMXEmitter::ASR (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(5, false, dest, src, op2);}
void ARMXEmitter::ASRS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(5, true, dest, src, op2);}

6
Core/MIPS/ARM/ArmCompALU.cpp
View File

@ -763,7 +763,11 @@ namespace MIPSComp
denominator >>= 1;
}
// The shift value is one too much for the divide by the same value.
LSR(gpr.R(MIPS_REG_LO), gpr.R(rs), shift - 1);
if (shift > 1) {
LSR(gpr.R(MIPS_REG_LO), gpr.R(rs), shift - 1);
} else {
MOV(gpr.R(MIPS_REG_LO), gpr.R(rs));
}
}
} else if (cpu_info.bIDIVa) {
// TODO: Does this handle INT_MAX, 0, etc. correctly?