From cb50075cf9a6f1510addcf5ebe07f3c2b57ecabd Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Mon, 22 Dec 2014 21:27:27 -0800 Subject: [PATCH] armjit: Correct NEON/non-VFPU reg allocation order. This fixes vh2f, which unbreaks games like Dissidia 012 and others. --- Core/MIPS/ARM/ArmRegCacheFPU.cpp | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.cpp b/Core/MIPS/ARM/ArmRegCacheFPU.cpp index 196123f58..2d883945c 100644 --- a/Core/MIPS/ARM/ArmRegCacheFPU.cpp +++ b/Core/MIPS/ARM/ArmRegCacheFPU.cpp @@ -90,6 +90,19 @@ const ARMReg *ArmRegCacheFPU::GetMIPSAllocationOrder(int &count) { // as the NEON instructions are all 2-vector or 4-vector, they don't do scalar, we want to be // able to use regular VFP instructions too. static const ARMReg allocationOrderNEON[] = { + // Reserve four temp registers. Useful when building quads until we really figure out + // how to do that best. + S4, S5, S6, S7, // Q1 + S8, S9, S10, S11, // Q2 + S12, S13, S14, S15, // Q3 + S16, S17, S18, S19, // Q4 + S20, S21, S22, S23, // Q5 + S24, S25, S26, S27, // Q6 + S28, S29, S30, S31, // Q7 + // Q8-Q15 free for NEON tricks + }; + + static const ARMReg allocationOrderNEONVFPU[] = { // Reserve four temp registers. Useful when building quads until we really figure out // how to do that best. S4, S5, S6, S7, // Q1 @@ -98,11 +111,16 @@ const ARMReg *ArmRegCacheFPU::GetMIPSAllocationOrder(int &count) { // Q4-Q15 free for VFPU }; + // NOTE: It's important that S2/S3 are not allocated with bNEON, even if !useNEONVFPU. + // They are used by a few instructions, like vh2f. if (jo_->useNEONVFPU) { - count = sizeof(allocationOrderNEON) / sizeof(const int); + count = sizeof(allocationOrderNEONVFPU) / sizeof(const ARMReg); + return allocationOrderNEONVFPU; + } else if (cpu_info.bNEON) { + count = sizeof(allocationOrderNEON) / sizeof(const ARMReg); return allocationOrderNEON; } else { - count = sizeof(allocationOrder) / sizeof(const int); + count = sizeof(allocationOrder) / sizeof(const ARMReg); return allocationOrder; } }