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more compiled alu
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@ -78,8 +78,34 @@ void Jit::Comp_RType2(u32 op) {
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Comp_Generic(op);
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}
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// Utilities to reduce duplicated code
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void Jit::CompImmLogic(int rs, int rt, u32 uimm, void (PPCXEmitter::*arith)(PPCReg Rd, PPCReg Ra, PPCReg Rb), u32 (*eval)(u32 a, u32 b)) {
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DebugBreak();
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}
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void Jit::CompType3(int rd, int rs, int rt, void (PPCXEmitter::*arith)(PPCReg Rd, PPCReg Ra, PPCReg Rb), u32 (*eval)(u32 a, u32 b), bool isSub) {
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, (*eval)(gpr.GetImm(rs), gpr.GetImm(rt)));
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} else if (gpr.IsImm(rt)) {
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u32 rtImm = gpr.GetImm(rt);
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gpr.MapDirtyIn(rd, rs);
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MOVI2R(SREG, rtImm);
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(this->*arith)(gpr.R(rd), gpr.R(rs), SREG);
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} else if (gpr.IsImm(rs)) {
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u32 rsImm = gpr.GetImm(rs);
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gpr.MapDirtyIn(rd, rt);
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// TODO: Special case when rsImm can be represented as an Operand2
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MOVI2R(SREG, rsImm);
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(this->*arith)(gpr.R(rd), SREG, gpr.R(rt));
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} else {
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// Generic solution
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gpr.MapDirtyInIn(rd, rs, rt);
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(this->*arith)(gpr.R(rd), gpr.R(rs), gpr.R(rt));
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}
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}
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void Jit::Comp_RType3(u32 op) {
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#if 0
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#if 1
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CONDITIONAL_DISABLE;
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int rt = _RT;
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int rs = _RS;
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@ -102,9 +128,25 @@ void Jit::Comp_RType3(u32 op) {
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gpr.MapDirtyIn(rd, rs);
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MR(gpr.R(rd), gpr.R(rs));
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} else {
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CompType3(rd, rs, rt, &ARMXEmitter::ADD, &EvalAdd);
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CompType3(rd, rs, rt, &PPCXEmitter::ADD, &EvalAdd);
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}
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break;
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// Crash
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/*
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case 34: //R(rd) = R(rs) - R(rt); break; //sub
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case 35: //R(rd) = R(rs) - R(rt); break; //subu
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CompType3(rd, rs, rt, &PPCXEmitter::SUB, &EvalSub, true);
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break;
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*/
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case 36: //R(rd) = R(rs) & R(rt); break; //and
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CompType3(rd, rs, rt, &PPCXEmitter::AND, &EvalAnd);
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break;
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case 37: //R(rd) = R(rs) | R(rt); break; //or
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CompType3(rd, rs, rt, &PPCXEmitter::OR, &EvalOr);
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break;
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case 38: //R(rd) = R(rs) ^ R(rt); break; //xor/eor
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CompType3(rd, rs, rt, &PPCXEmitter::XOR, &EvalEor);
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break;
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default:
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Comp_Generic(op);
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break;
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@ -215,7 +215,7 @@ namespace MIPSComp
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void Comp_Vfim(u32 op);
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// Utility compilation functions
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// Utility compilation functions
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void BranchFPFlag(u32 op, PpcGen::FixupBranchType cc, bool likely);
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void BranchVFPUFlag(u32 op, PpcGen::FixupBranchType cc, bool likely);
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void BranchRSZeroComp(u32 op, PpcGen::FixupBranchType cc, bool andLink, bool likely);
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@ -223,6 +223,10 @@ namespace MIPSComp
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void SetRegToEffectiveAddress(PpcGen::PPCReg r, int rs, s16 offset);
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// Utilities to reduce duplicated code
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void CompImmLogic(int rs, int rt, u32 uimm, void (PPCXEmitter::*arith)(PPCReg Rd, PPCReg Ra, PPCReg Rb), u32 (*eval)(u32 a, u32 b));
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void CompType3(int rd, int rs, int rt, void (PPCXEmitter::*arithOp2)(PPCReg Rd, PPCReg Ra, PPCReg Rb), u32 (*eval)(u32 a, u32 b), bool isSub = false);
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// flush regs
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void FlushAll();
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