diff --git a/Common/ArmEmitter.cpp b/Common/ArmEmitter.cpp
index d1a957485..ecfa13988 100644
--- a/Common/ArmEmitter.cpp
+++ b/Common/ArmEmitter.cpp
@@ -78,7 +78,7 @@ bool TryMakeOperand2_AllowNegation(s32 imm, Operand2 &op2, bool *negated)
 	}
 }
 
-void ARMXEmitter::ARMABI_MOVI2R(ARMReg reg, u32 val)
+void ARMXEmitter::MOVI2R(ARMReg reg, u32 val)
 {
 	Operand2 op2;
 	bool inverse;
@@ -117,7 +117,7 @@ void ARMXEmitter::ARMABI_MOVI2R(ARMReg reg, u32 val)
 }
 
 void ARMXEmitter::QuickCallFunction(ARMReg reg, void *func) {
-	ARMABI_MOVI2R(reg, (u32)(func));
+	MOVI2R(reg, (u32)(func));
 	BL(reg);
 }
 
diff --git a/Common/ArmEmitter.h b/Common/ArmEmitter.h
index 421d7e31b..f5be1f5d0 100644
--- a/Common/ArmEmitter.h
+++ b/Common/ArmEmitter.h
@@ -484,7 +484,7 @@ public:
 
 	void QuickCallFunction(ARMReg scratchreg, void *func);
 	// Utility functions
-	void ARMABI_MOVI2R(ARMReg reg, u32 val);
+	void MOVI2R(ARMReg reg, u32 val);
 	void ARMABI_ShowConditions();
 	void ARMABI_Return();
 
diff --git a/Core/MIPS/ARM/ArmAsm.cpp b/Core/MIPS/ARM/ArmAsm.cpp
index 0ebbc4a9e..d7d1e4b90 100644
--- a/Core/MIPS/ARM/ArmAsm.cpp
+++ b/Core/MIPS/ARM/ArmAsm.cpp
@@ -113,9 +113,9 @@ void Jit::GenerateFixedCode()
 	//   * downcount
 	//   * R2-R4
 	// Really starting to run low on registers already though...
-	ARMABI_MOVI2R(R11, (u32)Memory::base);
-	ARMABI_MOVI2R(R10, (u32)mips_);
-	ARMABI_MOVI2R(R9, (u32)GetBlockCache()->GetCodePointers());
+	MOVI2R(R11, (u32)Memory::base);
+	MOVI2R(R10, (u32)mips_);
+	MOVI2R(R9, (u32)GetBlockCache()->GetCodePointers());
 
 	outerLoop = GetCodePtr();
 		QuickCallFunction(R0, (void *)&CoreTiming::Advance);
@@ -127,7 +127,7 @@ void Jit::GenerateFixedCode()
 		// IMPORTANT - We jump on negative, not carry!!!
 		FixupBranch bailCoreState = B_CC(CC_MI);
 
-		ARMABI_MOVI2R(R0, (u32)&coreState);
+		MOVI2R(R0, (u32)&coreState);
 		LDR(R0, R0);
 		CMP(R0, 0);
 		FixupBranch badCoreState = B_CC(CC_NEQ);
@@ -172,7 +172,7 @@ void Jit::GenerateFixedCode()
 		SetJumpTarget(bail);
 		SetJumpTarget(bailCoreState);
 
-		ARMABI_MOVI2R(R0, (u32)&coreState);
+		MOVI2R(R0, (u32)&coreState);
 		LDR(R0, R0);
 		CMP(R0, 0);
 		B_CC(CC_EQ, outerLoop);
diff --git a/Core/MIPS/ARM/ArmCompALU.cpp b/Core/MIPS/ARM/ArmCompALU.cpp
index 3f9dc3b26..23a7096e8 100644
--- a/Core/MIPS/ARM/ArmCompALU.cpp
+++ b/Core/MIPS/ARM/ArmCompALU.cpp
@@ -47,7 +47,7 @@ namespace MIPSComp
 			if (TryMakeOperand2(uimm, op2)) {
 				(this->*arith)(gpr.R(rt), gpr.R(rs), op2);
 			} else {
-				ARMABI_MOVI2R(R0, (u32)uimm);
+				MOVI2R(R0, (u32)uimm);
 				(this->*arith)(gpr.R(rt), gpr.R(rs), R0);
 			}
 		}
@@ -80,7 +80,7 @@ namespace MIPSComp
 						else
 							SUB(gpr.R(rt), gpr.R(rs), op2);
 					} else {
-						ARMABI_MOVI2R(R0, (u32)simm);
+						MOVI2R(R0, (u32)simm);
 						ADD(gpr.R(rt), gpr.R(rs), R0);
 					}
 				}
@@ -102,13 +102,13 @@ namespace MIPSComp
 					else
 						CMN(gpr.R(rs), op2);
 				} else {
-					ARMABI_MOVI2R(R0, simm);
+					MOVI2R(R0, simm);
 					CMP(gpr.R(rs), R0);
 				}
 				SetCC(CC_LT);
-				ARMABI_MOVI2R(gpr.R(rt), 1);
+				MOVI2R(gpr.R(rt), 1);
 				SetCC(CC_GE);
-				ARMABI_MOVI2R(gpr.R(rt), 0);
+				MOVI2R(gpr.R(rt), 0);
 				SetCC(CC_AL);
 			}
 			break;
@@ -200,9 +200,9 @@ namespace MIPSComp
 			gpr.MapDirtyInIn(rd, rs, rt);
 			CMP(gpr.R(rs), gpr.R(rt));
 			SetCC(CC_LT);
-			ARMABI_MOVI2R(gpr.R(rd), 1);
+			MOVI2R(gpr.R(rd), 1);
 			SetCC(CC_GE);
-			ARMABI_MOVI2R(gpr.R(rd), 0);
+			MOVI2R(gpr.R(rd), 0);
 			SetCC(CC_AL);
 			break; 
 
@@ -210,9 +210,9 @@ namespace MIPSComp
 			gpr.MapDirtyInIn(rd, rs, rt);
 			CMP(gpr.R(rs), gpr.R(rt));
 			SetCC(CC_LO);
-			ARMABI_MOVI2R(gpr.R(rd), 1);
+			MOVI2R(gpr.R(rd), 1);
 			SetCC(CC_HS);
-			ARMABI_MOVI2R(gpr.R(rd), 0);
+			MOVI2R(gpr.R(rd), 0);
 			SetCC(CC_AL);
 			break;
 
diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp
index fb808c9a6..512ab9688 100644
--- a/Core/MIPS/ARM/ArmCompBranch.cpp
+++ b/Core/MIPS/ARM/ArmCompBranch.cpp
@@ -150,7 +150,7 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely
 	if (andLink)
 	{
 		ADD(R1, R10, MIPS_REG_RA * 4);  // compute address of RA in ram
-		ARMABI_MOVI2R(R0, js.compilerPC + 8);
+		MOVI2R(R0, js.compilerPC + 8);
 		STR(R1, R0);
 	}
 
@@ -281,7 +281,7 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely)
 
 	int imm3 = (op >> 18) & 7;
 
-	ARMABI_MOVI2R(R0, (u32)&(mips_->vfpuCtrl[VFPU_CTRL_CC]));
+	MOVI2R(R0, (u32)&(mips_->vfpuCtrl[VFPU_CTRL_CC]));
 	LDR(R0, R0, Operand2(0, TYPE_IMM));
 	TST(R0, Operand2(1 << imm3, TYPE_IMM));
 
@@ -344,7 +344,7 @@ void Jit::Comp_Jump(u32 op)
 
 	case 3: //jal
 		ADD(R1, R10, MIPS_REG_RA * 4);  // compute address of RA in ram
-		ARMABI_MOVI2R(R0, js.compilerPC + 8);
+		MOVI2R(R0, js.compilerPC + 8);
 		STR(R1, R0);
 		WriteExit(targetAddr, 0);
 		break;
@@ -393,7 +393,7 @@ void Jit::Comp_JumpReg(u32 op)
 		break;
 	case 9: //jalr
 		ADD(R1, R10, MIPS_REG_RA * 4);  // compute address of RA in ram
-		ARMABI_MOVI2R(R0, js.compilerPC + 8);
+		MOVI2R(R0, js.compilerPC + 8);
 		STR(R1, R0);
 		break;
 	default:
@@ -415,7 +415,7 @@ void Jit::Comp_Syscall(u32 op)
 	WriteDownCount(offset);
 	js.downcountAmount = -offset;
 
-	ARMABI_MOVI2R(R0, op);
+	MOVI2R(R0, op);
 	QuickCallFunction(R1, (void *)&CallSyscall);
 
 	WriteSyscallExit();
diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp
index 99b2a40f9..0a3be15da 100644
--- a/Core/MIPS/ARM/ArmCompLoadStore.cpp
+++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp
@@ -69,10 +69,10 @@ namespace MIPSComp
 			} else {
 				// Try to avoid using MOVT
 				if (offset < 0) {
-					ARMABI_MOVI2R(R0, (u32)(-offset));
+					MOVI2R(R0, (u32)(-offset));
 					SUB(R0, gpr.R(rs), R0);
 				} else {
-					ARMABI_MOVI2R(R0, (u32)offset);
+					MOVI2R(R0, (u32)offset);
 					ADD(R0, gpr.R(rs), R0);
 				}
 			}
@@ -105,7 +105,7 @@ namespace MIPSComp
 					// We can compute the full address at compile time. Kickass.
 					u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
 					gpr.MapReg(rt, MAP_NOINIT | MAP_DIRTY);  // must be OK even if rs == rt since we have the value from imm already.
-					ARMABI_MOVI2R(R0, addr);
+					MOVI2R(R0, addr);
 				} else {
 					gpr.MapDirtyIn(rt, rs);
 					SetR0ToEffectiveAddress(rs, offset);
@@ -133,7 +133,7 @@ namespace MIPSComp
 					// We can compute the full address at compile time. Kickass.
 					u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
 					gpr.MapReg(rt);
-					ARMABI_MOVI2R(R0, addr);
+					MOVI2R(R0, addr);
 				} else {
 					gpr.MapInIn(rt, rs);
 					SetR0ToEffectiveAddress(rs, offset);
diff --git a/Core/MIPS/ARM/ArmJit.cpp b/Core/MIPS/ARM/ArmJit.cpp
index eafd47de5..d34cb95f4 100644
--- a/Core/MIPS/ARM/ArmJit.cpp
+++ b/Core/MIPS/ARM/ArmJit.cpp
@@ -138,7 +138,7 @@ const u8 *Jit::DoJit(u32 em_address, ArmJitBlock *b)
 	b->checkedEntry = GetCodePtr();
 	// Downcount flag check. The last block decremented downcounter, and the flag should still be available.
 	SetCC(CC_LT);
-	ARMABI_MOVI2R(R0, js.blockStart);
+	MOVI2R(R0, js.blockStart);
 	MovToPC(R0);
 	B((const void *)outerLoop);
 	SetCC(CC_AL);
@@ -213,9 +213,9 @@ void Jit::Comp_Generic(u32 op)
 	MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
 	if (func)
 	{
-		ARMABI_MOVI2R(R0, js.compilerPC);
+		MOVI2R(R0, js.compilerPC);
 		MovToPC(R0);
-		ARMABI_MOVI2R(R0, op);
+		MOVI2R(R0, op);
 		QuickCallFunction(R1, (void *)func);
 	}
 }
@@ -240,7 +240,7 @@ void Jit::WriteDownCount(int offset)
 	} else {
 		// Should be fine to use R2 here, flushed the regcache anyway.
 		// If js.downcountAmount can be expressed as an Imm8, we don't need this anyway.
-		ARMABI_MOVI2R(R2, theDowncount);
+		MOVI2R(R2, theDowncount);
 		SUBS(R1, R1, R2);
 		STR(R10, R1, offsetof(MIPSState, downcount));
 	}
@@ -265,7 +265,7 @@ void Jit::WriteExit(u32 destination, int exit_num)
 		B(blocks.GetBlock(block)->checkedEntry);
 		b->linkStatus[exit_num] = true;
 	} else {
-		ARMABI_MOVI2R(R0, destination);
+		MOVI2R(R0, destination);
 		MovToPC(R0);
 		B((const void *)dispatcher);	
 	}
diff --git a/Core/MIPS/ARM/ArmJitCache.cpp b/Core/MIPS/ARM/ArmJitCache.cpp
index 6956625a1..62ec8fc49 100644
--- a/Core/MIPS/ARM/ArmJitCache.cpp
+++ b/Core/MIPS/ARM/ArmJitCache.cpp
@@ -354,7 +354,7 @@ void ArmJitBlockCache::DestroyBlock(int block_num, bool invalidate)
 	// I hope there's enough space...
 	// checkedEntry is the only "linked" entrance so it's enough to overwrite that.
 	ARMXEmitter emit((u8 *)b.checkedEntry);
-	emit.ARMABI_MOVI2R(R0, b.originalAddress);
+	emit.MOVI2R(R0, b.originalAddress);
 	emit.STR(R10, R0, offsetof(MIPSState, pc));
 	emit.B(MIPSComp::jit->dispatcher);
 	emit.FlushIcache();
diff --git a/Core/MIPS/ARM/ArmRegCache.cpp b/Core/MIPS/ARM/ArmRegCache.cpp
index 79287cb2b..6463e1349 100644
--- a/Core/MIPS/ARM/ArmRegCache.cpp
+++ b/Core/MIPS/ARM/ArmRegCache.cpp
@@ -92,7 +92,7 @@ allocate:
 						emit->MOV((ARMReg)reg, 0);
 					}
 				} else if (mr[mipsReg].loc == ML_IMM) {
-					emit->ARMABI_MOVI2R((ARMReg)reg, mr[mipsReg].imm);
+					emit->MOVI2R((ARMReg)reg, mr[mipsReg].imm);
 					ar[reg].isDirty = true;  // IMM is always dirty.
 				}
 			}
@@ -184,7 +184,7 @@ void ArmRegCache::FlushMipsReg(MIPSReg r) {
 	switch (mr[r].loc) {
 	case ML_IMM:
 		// IMM is always "dirty".
-		emit->ARMABI_MOVI2R(R0, mr[r].imm);
+		emit->MOVI2R(R0, mr[r].imm);
 		emit->STR(CTXREG, R0, GetMipsRegOffset(r));
 		break;
 
diff --git a/android/jni/ArmEmitterTest.cpp b/android/jni/ArmEmitterTest.cpp
index a035bcba7..b52a68e38 100644
--- a/android/jni/ArmEmitterTest.cpp
+++ b/android/jni/ArmEmitterTest.cpp
@@ -38,7 +38,7 @@ void TestCode::Generate()
 	testCodePtr = this->GetCodePtr();
 	// Sonic1 commented that R11 is the frame pointer in debug mode, whatever "debug mode" means.
 	PUSH(2, R11, _LR);
-	ARMABI_MOVI2R(R0, 0x13371338);
+	MOVI2R(R0, 0x13371338);
 	AND(R1, R0, Operand2(0xFC, 4));
 	BIC(R0, R0, Operand2(0xFC, 4));
 	CMP(R1, Operand2(0x10, 4));