From df50e03146a595a4d0b70e3cd8d4fcb5d4092780 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Wed, 14 Aug 2013 23:14:25 -0700 Subject: [PATCH] Add a safety log for cases we don't handle right. --- Core/MIPS/ARM/ArmCompBranch.cpp | 2 ++ Core/MIPS/x86/CompBranch.cpp | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp index 780ee1ea2..5f1d2bedf 100644 --- a/Core/MIPS/ARM/ArmCompBranch.cpp +++ b/Core/MIPS/ARM/ArmCompBranch.cpp @@ -282,6 +282,8 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely) CONDITIONAL_NICE_DELAYSLOT; if (!likely && delaySlotIsNice) CompileDelaySlot(DELAYSLOT_NICE); + if (delaySlotIsBranch && (delaySlotOp & 0xFFFF) != offset - 1) + ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target", js.compilerPC); FlushAll(); diff --git a/Core/MIPS/x86/CompBranch.cpp b/Core/MIPS/x86/CompBranch.cpp index a5b773c04..568fdbd22 100644 --- a/Core/MIPS/x86/CompBranch.cpp +++ b/Core/MIPS/x86/CompBranch.cpp @@ -357,6 +357,8 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely) CONDITIONAL_NICE_DELAYSLOT; if (!likely && delaySlotIsNice) CompileDelaySlot(DELAYSLOT_NICE); + if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1) + ERROR_LOG(JIT, "VFPU branch in VFPU delay slot at %08x with different target %d / %d", js.compilerPC, (signed short)(delaySlotOp & 0xFFFF), (signed short)(op & 0xFFFF) - 1); FlushAll();