From f1b11c63fc903138d90add4dbbadc9bbaf6c7ec2 Mon Sep 17 00:00:00 2001 From: Ced2911 Date: Mon, 26 Aug 2013 17:47:20 +0200 Subject: [PATCH] add some shifs instruction, fixes some instructions --- Common/ppcEmitter.cpp | 54 +++++++++++++++++++++++++++++++++++-------- Common/ppcEmitter.h | 22 ++++++++++++------ 2 files changed, 59 insertions(+), 17 deletions(-) diff --git a/Common/ppcEmitter.cpp b/Common/ppcEmitter.cpp index a06d91e1f..30c4aef27 100644 --- a/Common/ppcEmitter.cpp +++ b/Common/ppcEmitter.cpp @@ -1,6 +1,12 @@ #include #include "ppcEmitter.h" +// Helper +#define X_FORM(OPCD, D, A, B, XO, Rc) { \ + int a = (A), b = (B), d = (D); \ + Write32((OPCD << 26) | (d << 21) | (a << 16) | (b << 11) | (((XO) & 0x3ff) << 1) | (Rc)); \ +} + namespace PpcGen { // Arithmetics ops @@ -24,13 +30,13 @@ namespace PpcGen { Write32(instr); } - void PPCXEmitter::ANDI (PPCReg Rd, PPCReg Ra, unsigned short imm) { - u32 instr = (0x70000000 | (Rd << 21) | (Ra << 16) | ((imm) & 0xffff)); + void PPCXEmitter::ANDI (PPCReg Rdest, PPCReg Ra, unsigned short imm) { + u32 instr = (0x70000000 | (Ra << 21) | (Rdest << 16) | ((imm) & 0xffff)); Write32(instr); } - void PPCXEmitter::ANDIS (PPCReg Rd, PPCReg Ra, unsigned short imm) { - u32 instr = (0x74000000 | (Rd << 21) | (Ra << 16) | ((imm) & 0xffff)); + void PPCXEmitter::ANDIS (PPCReg Rdest, PPCReg Ra, unsigned short imm) { + u32 instr = (0x74000000 | (Ra << 21) | (Rdest << 16) | ((imm) & 0xffff)); Write32(instr); } @@ -353,18 +359,18 @@ namespace PpcGen { } // Others operation - void PPCXEmitter::ORI(PPCReg src, PPCReg dest, unsigned short imm) { - u32 instr = (0x60000000 | (src << 21) | (dest << 16) | (imm & 0xffff)); + void PPCXEmitter::ORI(PPCReg Rd, PPCReg Ra, unsigned short imm) { + u32 instr = (0x60000000 | (Ra << 21) | (Rd << 16) | (imm & 0xffff)); Write32(instr); } - void PPCXEmitter::XORI (PPCReg src, PPCReg dest, unsigned short imm) { - u32 instr = (0x68000000 | (src << 21) | (dest << 16) | (imm & 0xffff)); + void PPCXEmitter::XORI (PPCReg Rdest, PPCReg Ra, unsigned short imm) { + u32 instr = (0x68000000 | (Ra << 21) | (Rdest << 16) | (imm & 0xffff)); Write32(instr); } - void PPCXEmitter::OR(PPCReg Rd, PPCReg Ra, PPCReg Rb) { - u32 instr = (0x7C000378 | (Ra << 21) | (Rd << 16) | (Rb << 11)); + void PPCXEmitter::OR(PPCReg Rdest, PPCReg Ra, PPCReg Rb) { + u32 instr = (0x7C000378 | (Ra << 21) | (Rdest << 16) | (Rb << 11)); Write32(instr); } @@ -372,6 +378,12 @@ namespace PpcGen { u32 instr = (0x7C000278 | (Ra << 21) | (Rd << 16) | (Rb << 11)); Write32(instr); } + + + void PPCXEmitter::NOR(PPCReg Rd, PPCReg Ra, PPCReg Rb) { + u32 instr = (0x7C0000f8 | (Ra << 21) | (Rd << 16) | (Rb << 11)); + Write32(instr); + } void PPCXEmitter::SUBF(PPCReg Rd, PPCReg Ra, PPCReg Rb, int RCFlags) { u32 instr = (0x7C000050 | (Rd << 21) | (Ra << 16) | (Rb << 11) | (RCFlags & 1)); @@ -419,6 +431,28 @@ namespace PpcGen { Write32((21<<26) | (src << 21) | (dest << 16) | (shift << 11) | (start << 6) | (end << 1)); } + // Shift Instructions + void PPCXEmitter::SRAW (PPCReg dest, PPCReg src, PPCReg shift) { + X_FORM(31, src, dest, shift, 792, 0); + } + void PPCXEmitter::SRAWI (PPCReg dest, PPCReg src, unsigned short imm) { + X_FORM(31, src, dest, imm, 824, 0); + } + + void PPCXEmitter::SLW (PPCReg dest, PPCReg src, PPCReg shift) { + X_FORM(31, src, dest, shift, 24, 0); + } + void PPCXEmitter::SLWI (PPCReg dest, PPCReg src, unsigned short imm) { + RLWINM(dest, src, imm, 0, (31-imm)); + } + + void PPCXEmitter::SRW (PPCReg dest, PPCReg src, PPCReg shift) { + X_FORM(31, src, dest, shift, 536, 0); + } + void PPCXEmitter::SRWI (PPCReg dest, PPCReg src, unsigned short imm) { + RLWINM(dest, src, (32-imm), imm, 31); + } + // Prologue / epilogue void PPCXEmitter::Prologue() { diff --git a/Common/ppcEmitter.h b/Common/ppcEmitter.h index 511ac7e8e..39d436623 100644 --- a/Common/ppcEmitter.h +++ b/Common/ppcEmitter.h @@ -141,7 +141,6 @@ namespace PpcGen protected: // Write opcode inline void Write32(u32 value) {*(u32*)code = value; code+=4;} - public: PPCXEmitter() : code(0), startcode(0), lastCacheFlushEnd(0) { } @@ -212,13 +211,14 @@ namespace PpcGen // Logical Ops void AND (PPCReg Rs, PPCReg Ra, PPCReg Rb); - void ANDI (PPCReg Rs, PPCReg Ra, unsigned short imm); - void ANDIS(PPCReg Rs, PPCReg Ra, unsigned short imm); + void ANDI (PPCReg Rdest, PPCReg Ra, unsigned short imm); + void ANDIS(PPCReg Rdest, PPCReg Ra, unsigned short imm); void NAND (PPCReg Rs, PPCReg Ra, PPCReg Rb); void OR (PPCReg Rs, PPCReg Ra, PPCReg Rb); - void ORC (PPCReg Rs, PPCReg Ra, PPCReg Rb); + void ORI (PPCReg Rdest, PPCReg Ra, unsigned short imm); void NOR (PPCReg Rs, PPCReg Ra, PPCReg Rb); void XOR (PPCReg Rs, PPCReg Ra, PPCReg Rb); + void XORI (PPCReg Rdest, PPCReg Ra, unsigned short imm); void NEG (PPCReg Rs, PPCReg Ra, PPCReg Rb); // Arithmetics ops @@ -241,9 +241,6 @@ namespace PpcGen void MULHW (PPCReg dest, PPCReg src, PPCReg op2); void MULHWS(PPCReg dest, PPCReg src, PPCReg op2); - void ORI (PPCReg src, PPCReg dest, unsigned short imm); - void XORI (PPCReg src, PPCReg dest, unsigned short imm); - // Memory load/store operations void LI (PPCReg dest, unsigned short imm); void LIS (PPCReg dest, unsigned short imm); @@ -280,8 +277,19 @@ namespace PpcGen void EXTSB (PPCReg dest, PPCReg src); void EXTSH (PPCReg dest, PPCReg src); + // void RLWINM (PPCReg dest, PPCReg src, int shift, int start, int end); + // Shift Instructions + void SRAW (PPCReg dest, PPCReg src, PPCReg shift); + void SRAWI (PPCReg dest, PPCReg src, unsigned short imm); + + void SLW (PPCReg dest, PPCReg src, PPCReg shift); + void SLWI (PPCReg dest, PPCReg src, unsigned short imm); + + void SRW (PPCReg dest, PPCReg src, PPCReg shift); + void SRWI (PPCReg dest, PPCReg src, unsigned short imm); + // Compare void CMPLI (PPCReg dest, unsigned short imm); void CMPI (PPCReg dest, unsigned short imm);