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Merge pull request #4428 from Kingcom/StepOver
Fix step over handling of fpu branches and jalr
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commit
f414856ebe
@ -404,7 +404,7 @@ namespace MIPSAnalyst {
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//j , jal, ...
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if (opInfo & IS_JUMP) {
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info.isBranch = true;
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if (opInfo & OUT_RA) { // link
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if ((opInfo & OUT_RA) || (opInfo & OUT_RD)) { // link
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info.isLinkedBranch = true;
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}
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@ -446,15 +446,23 @@ namespace MIPSAnalyst {
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u32 rs = cpu->GetRegValue(0, (int)MIPS_GET_RS(op));
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switch (opInfo & CONDTYPE_MASK) {
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case CONDTYPE_EQ:
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info.conditionMet = (rt == rs);
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if (MIPS_GET_RT(op) == MIPS_GET_RS(op)) { // always true
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info.isConditional = false;
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if (opInfo & IN_FPUFLAG) { // fpu branch
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info.conditionMet = currentMIPS->fpcond == 0;
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} else {
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info.conditionMet = (rt == rs);
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if (MIPS_GET_RT(op) == MIPS_GET_RS(op)) { // always true
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info.isConditional = false;
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}
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}
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break;
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case CONDTYPE_NE:
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info.conditionMet = (rt != rs);
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if (MIPS_GET_RT(op) == MIPS_GET_RS(op)) { // always true
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info.isConditional = false;
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if (opInfo & IN_FPUFLAG) { // fpu branch
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info.conditionMet = currentMIPS->fpcond != 0;
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} else {
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info.conditionMet = (rt != rs);
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if (MIPS_GET_RT(op) == MIPS_GET_RS(op)) { // always true
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info.isConditional = false;
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}
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}
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break;
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case CONDTYPE_LEZ:
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@ -437,10 +437,10 @@ const MIPSInstruction tableCop1[32] = // 010001 xxxxx ..... ..... ...........
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const MIPSInstruction tableCop1BC[32] = // 010001 01000 xxxxx ................
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{
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INSTR("bc1f", &Jit::Comp_FPUBranch, Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT),
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INSTR("bc1t", &Jit::Comp_FPUBranch, Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT),
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INSTR("bc1fl", &Jit::Comp_FPUBranch, Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|LIKELY),
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INSTR("bc1tl", &Jit::Comp_FPUBranch, Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|LIKELY),
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INSTR("bc1f", &Jit::Comp_FPUBranch, Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|CONDTYPE_FPUFALSE),
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INSTR("bc1t", &Jit::Comp_FPUBranch, Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|CONDTYPE_FPUTRUE),
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INSTR("bc1fl", &Jit::Comp_FPUBranch, Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|LIKELY|CONDTYPE_FPUFALSE),
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INSTR("bc1tl", &Jit::Comp_FPUBranch, Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|LIKELY|CONDTYPE_FPUTRUE),
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INVALID, INVALID, INVALID, INVALID,
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//8
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INVALID_X_8,
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@ -43,6 +43,9 @@ struct MIPSInfo {
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#define CONDTYPE_LTZ 0x00000005
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#define CONDTYPE_GEZ 0x00000006
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#define CONDTYPE_FPUFALSE CONDTYPE_EQ
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#define CONDTYPE_FPUTRUE CONDTYPE_NE
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// as long as the other flags are checked,
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// there is no way to misinterprete these
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// as CONDTYPE_X
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