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Cleanup

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This commit is contained in:
Henrik Rydgard 2013-01-09 00:12:02 +01:00
parent 76481a300c
commit f5c94775b9
8 changed files with 17 additions and 28 deletions
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2
Core/Core.cpp
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@ -65,7 +65,6 @@ bool Core_IsStepping()
void Core_RunLoop()
{
currentMIPS->RunLoopUntil(0xFFFFFFFFFFFFFFFULL);
INFO_LOG(DYNA_REC, "Wooo");
}
void Core_DoSingleStep()
@ -94,7 +93,6 @@ reswitch:
case CORE_RUNNING:
//1: enter a fast runloop
Core_RunLoop();
INFO_LOG(DYNA_REC, "Yay");
break;
// We should never get here on Android.

1
Core/HLE/sceDisplay.cpp
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@ -269,7 +269,6 @@ void hleEnterVblank(u64 userdata, int cyclesLate) {
// Tell the emu core that it's time to stop emulating
// Win32 doesn't need this.
#ifndef _WIN32
ERROR_LOG(HLE, "End oph phrame");
coreState = CORE_NEXTFRAME;
#endif
}

7
Core/MIPS/ARM/ArmAsm.cpp
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@ -176,9 +176,10 @@ void ArmAsmRoutineManager::Generate(MIPSState *mips, MIPSComp::Jit *jit)
POP(9, R4, R5, R6, R7, R8, R9, R10, R11, _PC); // Returns
INFO_LOG(HLE, "THE DISASM ========================");
DisassembleArm(enterCode, GetCodePtr() - enterCode);
INFO_LOG(HLE, "END OF THE DISASM ========================");
// Uncomment if you want to see the output...
// INFO_LOG(HLE, "THE DISASM ========================");
// DisassembleArm(enterCode, GetCodePtr() - enterCode);
// INFO_LOG(HLE, "END OF THE DISASM ========================");
// Don't forget to zap the instruction cache!
FlushIcache();

22
Core/MIPS/ARM/ArmCompBranch.cpp
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@ -63,19 +63,21 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
}
// The delay slot being nice doesn't really matter though...
if (rt == 0)
/*
if (rt == 0)
{
gpr.MapReg(rs, MAP_INITVAL);
CMP(gpr.R(rs), Operand2(0));
CMP(gpr.R(rs), Operand2(0, TYPE_IMM));
}
/*
else if (rs == 0 && (cc == CC_EQ || cc == CC_NEQ)) // only these are easily 'flippable'
{
gpr.MapReg(rt, MAP_INITVAL);
CMP(gpr.R(rt), Operand2(0));
}
else
*/
else {
{
gpr.SpillLock(rs, rt);
gpr.MapReg(rs, MAP_INITVAL);
gpr.MapReg(rt, MAP_INITVAL);
@ -135,7 +137,7 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool likely)
// ERROR_LOG(CPU, "Not nice delay slot in BranchRSZeroComp :( %08x", js.compilerPC);
}
gpr.MapReg(rs, MAP_INITVAL);
CMP(gpr.R(rs), Operand2(0));
CMP(gpr.R(rs), Operand2(0, TYPE_IMM));
FlushAll();
ArmGen::FixupBranch ptr;
@ -228,7 +230,7 @@ void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely)
FlushAll();
LDR(R0, R10, offsetof(MIPSState, fpcond));
CMP(R0, Operand2(1, TYPE_IMM));
TST(R0, Operand2(1, TYPE_IMM));
ArmGen::FixupBranch ptr;
js.inDelaySlot = true;
if (!likely)
@ -262,10 +264,10 @@ void Jit::Comp_FPUBranch(u32 op)
{
switch((op >> 16) & 0x1f)
{
case 0: BranchFPFlag(op, CC_EQ, false); break; // bc1f
case 1: BranchFPFlag(op, CC_NEQ, false); break; // bc1t
case 2: BranchFPFlag(op, CC_EQ, true); break; // bc1fl
case 3: BranchFPFlag(op, CC_NEQ, true); break; // bc1tl
case 0: BranchFPFlag(op, CC_NEQ, false); break; // bc1f
case 1: BranchFPFlag(op, CC_EQ, false); break; // bc1t
case 2: BranchFPFlag(op, CC_NEQ, true); break; // bc1fl
case 3: BranchFPFlag(op, CC_EQ, true); break; // bc1tl
default:
_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
break;

3
Core/MIPS/ARM/ArmJit.cpp
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@ -84,7 +84,6 @@ void Jit::CompileAt(u32 addr)
void Jit::Compile(u32 em_address)
{
ERROR_LOG(CPU, "Compile %08x", em_address);
if (GetSpaceLeft() < 0x10000 || blocks.IsFull())
{
ClearCache();
@ -99,8 +98,6 @@ void Jit::RunLoopUntil(u64 globalticks)
{
// TODO: copy globalticks somewhere
((void (*)())asm_.enterCode)();
INFO_LOG(DYNA_REC, "Left asm code like a boss!");
INFO_LOG(DYNA_REC, "or Two!");
}
const u8 *Jit::DoJit(u32 em_address, ArmJitBlock *b)

6
Core/MIPS/x86/CompBranch.cpp
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@ -343,11 +343,6 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely)
void Jit::Comp_VBranch(u32 op)
{
// _dbg_assert_msg_(CPU,0,"comp_vbranch not supported");
//int imm = (signed short)(op&0xFFFF)<<2;
//u32 targetAddr = js.compilerPC + imm + 4;
switch ((op >> 16) & 3)
{
case 0: BranchVFPUFlag(op, CC_NZ, false); break; //bvf
@ -369,7 +364,6 @@ void Jit::Comp_Jump(u32 op)
}
u32 off = ((op & 0x3FFFFFF) << 2);
u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
//Delay slot
CompileAt(js.compilerPC + 4);
FlushAll();

3
Windows/main.cpp
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@ -51,9 +51,6 @@ CMemoryDlg *memoryWindow[MAX_CPUCOUNT];
int WINAPI WinMain(HINSTANCE _hInstance, HINSTANCE hPrevInstance, LPSTR szCmdLine, int iCmdShow)
{
char temp[256];
ArmDis(0, 0xE12fff10, temp);
Common::EnableCrashingOnCrashes();
const char *fileToStart = NULL;

1
android/jni/NativeApp.cpp
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@ -192,6 +192,7 @@ void NativeInit(int argc, const char *argv[], const char *savegame_directory, co
switch (argv[i][1]) {
case 'd':
// Enable debug logging
// Note that you must also change the max log level in Log.h.
logLevel = LogTypes::LDEBUG;
break;
case 'g':