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Whitelist common delay slot ops with outreg info.

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This commit is contained in:
Unknown W. Brackets 2013-01-24 19:59:33 -08:00
parent d1909a1581
commit f7ebddc4a3
2 changed files with 33 additions and 5 deletions
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36
Core/MIPS/MIPSAnalyst.cpp
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@ -86,15 +86,43 @@ namespace MIPSAnalyst
}
}
bool IsDelaySlotNiceReg(u32 branchOp, u32 op, u32 reg1, u32 reg2)
// Temporary, returns true for common ops which have proper flags in the table.
bool IsDelaySlotInfoSafe(u32 op)
{
const char *safeOps[] = {
"addi", "addiu", "slti", "sltiu", "andi", "ori", "xori", "lui",
"lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr",
"sb", "sh", "swl", "sw", "swr",
"add", "addu", "sub", "subu", "and", "or", "xor", "nor",
"slt", "sltu",
};
const char *opName = MIPSGetName(op);
for (int i = 0; i < ARRAY_SIZE(safeOps); ++i)
{
if (!strcmp(safeOps[i], opName))
return true;
}
return false;
}
bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2)
{
// NOOPs are always nice.
if (op == 0)
return true;
// TODO: Something like this?
//if (GetOutReg(op) != reg1 && GetOutReg(op) != reg2)
// return true;
// TODO: Once the flags are all correct on the tables, remove this safety.
if (IsDelaySlotInfoSafe(op))
{
// $0 is never an out reg, it's always 0.
if (reg1 != 0 && GetOutReg(op) == reg1)
return false;
if (reg2 != 0 && GetOutReg(op) == reg2)
return false;
return true;
}
return false;
}

2
Core/MIPS/MIPSAnalyst.h
View File

@ -57,7 +57,7 @@ namespace MIPSAnalyst
int GetOutReg(u32 op);
bool ReadsFromReg(u32 op, u32 reg);
bool IsDelaySlotNice(u32 branch, u32 delayslot);
bool IsDelaySlotNiceReg(u32 branchOp, u32 op, u32 reg1, u32 reg2 = 0xFF);
bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2 = 0);
bool IsDelaySlotNiceVFPU(u32 branchOp, u32 op);
bool IsDelaySlotNiceFPU(u32 branchOp, u32 op);
bool IsSyscall(u32 op);