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601 Commits

Author SHA1 Message Date
Unknown W. Brackets
98d7afae89 Switch to #pragma once in a few places. 
Doesn't really affect git history much to change these.
 2015-03-02 22:34:51 -08:00
Unknown W. Brackets
179e996b0b jit: Discard unused regs before a syscall. 
This is a pretty minor optimization, though.
 2015-03-01 11:08:59 -08:00
Chin
37f50a3792 Change to pass some arguments by reference 2015-03-01 16:49:00 +01:00
Henrik Rydgard
07933cad42 Revert "Minor optimizations, add a failsafe" 
This reverts commit 48e4d1edae19a2f7e3761e9ff7dc93ed63db7de9.
 2015-01-22 19:52:58 +01:00
Henrik Rydgard
48e4d1edae Minor optimizations, add a failsafe 2015-01-20 20:08:12 +01:00
Unknown W. Brackets
cdddd4b59c Fix an undefined bit shift. 
Shouldn't have mattered anyway, but maybe this can crash some ARM chip or
something...
 2015-01-19 08:40:10 -08:00
Unknown W. Brackets
9cb1151b67 x86jit: Disable replacements w/ breakpoints inside. 
This does alter graphics (memcpys won't fire anymore), but it also means
breakpoints work which is nice.
 2015-01-18 21:26:37 -08:00
Unknown W. Brackets
0dc3e4e2db x86jit: Handle unable to spill better. 
Might as well check the result to be safe.
 2015-01-17 18:42:58 -08:00
Unknown W. Brackets
a27be3887e x86jit: Handle overlap better in simd vtfm. 2015-01-07 18:10:53 -08:00
Henrik Rydgård
bb1d571493 Merge pull request #7261 from hilesaz/master 
Fix simd vmmul transpose optimizations.
 2015-01-06 11:59:14 +01:00
Unknown W. Brackets
23893ffba8 x86jit: Fix crash in prefixes and simd enabled. 2015-01-04 15:50:12 -08:00
Henrik Rydgard
90376267b1 More reg number asserts 2015-01-04 23:15:33 +01:00
Henrik Rydgard
fe63a15e22 x86jit fpu regcache: Add extra invariant check for too-large mips register numbers 2015-01-04 22:54:01 +01:00
Bovine
54c7a12306 Fix simd vmmul transpose optimizations. 
Yep, gotta discard the S matrix when we're done with it.
 2015-01-03 16:58:03 -07:00
Bovine
0fdebdc1ca Fix discardVS. 
It's not valid for non-away values to have a lane.
 2015-01-03 16:54:31 -07:00
Henrik Rydgard
3cc633f091 x86jit: Minor logging improvements in FPU recache 2015-01-03 22:55:39 +01:00
Bovine
185d4db081 Fix simd vmmul transpose optimizations. 
Need to ensure S has been written back before transposing it or we'll end
up writing back S'.
 2015-01-03 14:48:54 -07:00
Henrik Rydgård
5fffe53671 Merge pull request #7258 from unknownbrackets/jit-minor 
x86jit: Fix vavg, improve vfad
 2015-01-03 19:44:22 +01:00
Unknown W. Brackets
a1864b2c78 x86jit: Fix vavg scale. 
Was completely wrong, darn it.
 2015-01-03 10:39:58 -08:00
Unknown W. Brackets
8a089ee583 x86jit: Handle -0.0 in vavg/vfad. 
Should result in a positive result.
 2015-01-03 10:39:26 -08:00
Henrik Rydgard
13c4a22967 Disable transpose optimization, seems to break games 2015-01-02 01:13:34 +01:00
Henrik Rydgard
6a7e5d1cc2 x86 Jit SIMD: Generate somewhat shorter code for handling transposed matrices in vmmul. 
TODO: Build into regalloc instead, with a MapMatrix function?
 2015-01-01 12:44:03 +01:00
Unknown W. Brackets
5f6f8ac0a2 x86jit: Fix another sequential detect problem. 
Arg.  Maybe should use voffset after all, but it won't fit in a u8
anyway...
 2014-12-31 22:43:31 -08:00
Unknown W. Brackets
c5f7b6fa72 x86jit: Disable simd again for now. 2014-12-31 19:43:40 -08:00
Henrik Rydgård
6bf2c02908 x86 jit: Allow storing all imms directly without bouncing to a register, not just zero. 2014-12-23 22:25:53 +01:00
Bovine
a9b7656f93 Fix to VFPU register allocation. Fixes #7174 
GetFreeXRegs(_,_,true) invalidates registers it can see on spill,
but it can't see all the registers in the array due to how we call it
so we have to invalidate the rest ourselves.  Not doing so can get it
to use the same register twice.
 2014-12-23 03:39:50 -07:00
Unknown W. Brackets
a514603f40 Fix some missing case warnings. 2014-12-20 09:10:09 -08:00
Unknown W. Brackets
a292fa87ea x86jit: Fix an x32 compile error in disabled code. 2014-12-17 08:50:31 -08:00
Unknown W. Brackets
2743c5cacd x86jit: Shave off a couple bytes in asm. 2014-12-17 08:25:18 -08:00
Unknown W. Brackets
77777e372d x86jit: Use R15 when safe for the jit. 
This is virtually always safe.
 2014-12-17 08:09:59 -08:00
Unknown W. Brackets
b9eddc3d25 x86jit: Oops, fix a typesafety error. 2014-12-17 08:07:43 -08:00
Unknown W. Brackets
9022b48069 x86jit: Skip reload of EAX in safe cases. 
Probably no real improvement in perf, but a bit cleaner and one less TODO.
 2014-12-17 01:12:41 -08:00
Unknown W. Brackets
afdbf5610b jit: Use nicknames for a few more static regs. 2014-12-17 01:11:33 -08:00
Unknown W. Brackets
b6a75bf255 x86jit: Set CTXREG in a fixed place. 2014-12-17 01:00:21 -08:00
Henrik Rydgard
05a8e2e35d Some work towards being able to build two JITs together 
This will be useful for testing/debugging, but not there yet.
 2014-12-13 21:13:54 +01:00
Henrik Rydgard
8ad1ea4c84 Split JitCommon.h so that you can include it without getting the "NativeJit" definition 2014-12-13 21:13:28 +01:00
Henrik Rydgård
5ae4cc8959 x86: Turn VFPU SIMD off again. See #7173 and #7174 2014-12-13 13:35:29 +01:00
Unknown W. Brackets
afc779a824 jit: Add IN_RT to lwl/lwr and re-enable clobbering. 2014-12-08 21:17:01 -08:00
Unknown W. Brackets
bfe5f9276e jit: Re-disable clobbered thing. 
No idea what's wrong...
 2014-12-08 02:06:25 -08:00
Unknown W. Brackets
7734a4c912 jit: Re-enable clobbering with movz/movn support. 
Oops, these should be the only ones that take rd "in".
 2014-12-08 01:29:41 -08:00
Unknown W. Brackets
119c1ef83e jit: Disable clobber detection for now. 
Should still spill better.  Something is wrong with flags detection, a
clobber to rd is incorrectly discarding outside a delay slot.  Don't have
time now to look into it further.
 2014-12-08 01:24:17 -08:00
Unknown W. Brackets
f817d49dfb jit: Discard clobbered registers on spill. 
If we're spilling anyway, discard rather than saving.
 2014-12-07 23:08:21 -08:00
Unknown W. Brackets
eeff110c0f jit: Improve and unify GPR spill logic. 
Now the same logic on x86 and ARM, and handles HI/LO/etc. better.
 2014-12-07 21:10:28 -08:00
Unknown W. Brackets
9dd6bb56bb jit: Make available js_ and jo_ in regcaches. 2014-12-07 21:07:23 -08:00
Henrik Rydgard
51d55bd645 Namespacing cleanup (it's bad to do "using namespace" in a header) 2014-12-07 14:44:15 +01:00
Henrik Rydgard
7740caeade Buildfix the arm emitter test in the unittest. 
Also do some preparation for being able to have two JITs compiled at the same time
which may be useful in testing parts of the ARM jit on Windows.
 2014-12-07 14:12:13 +01:00
Henrik Rydgard
d46c9c2f74 x86 jit: Minor optimization in vmmul 2014-12-06 11:35:01 +01:00
Henrik Rydgard
ea6371921a x86 jit: Hack around running out of regs on x86-32 with SIMD 2014-12-04 00:19:08 +01:00
Henrik Rydgard
e3a81f4346 x86 Jit: Basic implementation of vbfy1/2 (mostly to just cross another one off the list..) 2014-12-04 00:18:58 +01:00
Henrik Rydgard
5290ffd929 Minor cleanup in vtfm. Re-enable vrot combination. Optimize vfad/vavg when dpps is available. 
Also fixes bug in emitter of dpps.
 2014-12-03 22:44:32 +01:00