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10,291 Commits 19 Branches 54 Tags 247 MiB
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368 Commits

Author SHA1 Message Date
Henrik Rydgard
4e0520131a Tiny optimization 2013-11-15 20:32:23 +01:00
Henrik Rydgard
d17a5fefea ARM: Fix divide by 0 in software divide used on CPUs without HW divide. 2013-11-15 20:24:20 +01:00
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5128083d93 Mask out fcr31 bits that can't be set on a PSP. 2013-11-14 23:57:28 -08:00
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3c73d0d1f1 armjit: Read fpu control regs other than 0/31 as 0. 
Always seem to give zero, regardless of the value of fcr31, etc.
 2013-11-14 23:39:39 -08:00
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763eff181d Fix handling of jalr when delay slot changes rd. 2013-11-14 23:39:13 -08:00
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26f5922174 Return the correct value for fcr0/fir. 
This is what the PSP actually returns, it's read only.
 2013-11-14 23:39:08 -08:00
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98fb2e0402 armjit: Refer to R11 as MEMBASEREG for clarity. 2013-11-14 23:37:48 -08:00
Sacha
e3bdb3e09b Disable LitPool as it is causing crashes with Vertex Decoder JIT. Performance seems to be almost unaffected since the IMM changes. 2013-11-15 14:12:00 +10:00
Sacha
20e8a81268 Switch to compile-time ARMV7 define. 2013-11-15 11:20:39 +10:00
Henrik Rydgard
9a14d33372 Disable software divide that appears to be buggy, see #4539 2013-11-14 17:25:02 +01:00
Henrik Rydgård
ef8631c57f Cache VFPU_CTRL_CC in a register 2013-11-12 17:58:29 +01:00
Henrik Rydgard
df3765a320 Arm jit: optimize ES, NS conditions in vcmp. Bugfix TR. 2013-11-12 14:43:12 +01:00
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f4b5e8a4c1 Merge pull request #4518 from hrydgard/fpcond 
ARMJIT: Cache fpcond in a register to avoid store/load between compare and branch
 2013-11-12 01:50:16 -08:00
Henrik Rydgård
17074f5a7f Cache fpcond in a register to avoid store/load between compare and branch 2013-11-12 10:33:38 +01:00
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32504ed46e armjit: Prioritize spilling regs not used soon. 
This may improve trashing.
 2013-11-12 00:03:39 -08:00
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1bfce12fdd armjit: Report some unexpected situations. 2013-11-11 23:41:18 -08:00
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ac5aacbd16 armjit: Spill an imm armreg back to an imm. 
We might be able to avoid the store or etc.
 2013-11-11 23:39:13 -08:00
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bb960480c8 x86/armjit: Stop compiling on a jump to invalid. 2013-11-10 21:59:50 -08:00
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359110f010 x86/armjit: Add jump following (off by default.) 
Inlines function calls up to a certain extent.  Allows us to get
immediates all the way to a syscall, for example, usually.

Not sure if faster.
 2013-11-10 21:59:49 -08:00
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aacb31bc18 armjit: Copy over (disabled) immbranch optim. 
This does a little loop unrolling.  Costs a bit more cache space, but
avoids flushing regs for longer.

Not enabled.
 2013-11-10 21:59:48 -08:00
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92ecff4396 armjit: keep track of instructions in jitstate. 
To match x86.
 2013-11-10 21:59:48 -08:00
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8ceaafc159 armjit: Verify free space while compiling. 2013-11-10 21:59:48 -08:00
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ca7b2b554b armjit: fix major typo breaking mult/multu. 2013-11-10 21:54:44 -08:00
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e1fffdb37a armjit: Don't reload an armreg ptr marked noinit. 2013-11-10 16:43:38 -08:00
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67eaa2fd1c armjit: Optimize immediate load/stores in a row. 2013-11-10 16:32:48 -08:00
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bc0a846475 armjit: Optimize imm addresses (could do better...) 2013-11-10 16:30:20 -08:00
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c63560c0dd armjit: Try to find imms to optimize a reg load. 
This way we skip the MOVW/MOVT and go for one op only.
 2013-11-10 16:20:34 -08:00
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7e46ee0b0f armjit: Replace MOVI2R with using the regcache. 
So that it can optimize the value with existing imms.

Not actually optimizing yet.
 2013-11-10 15:50:45 -08:00
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d092f7dd2d armjit: Remember reg imm values even after flush. 
This way, we can base other imm values off them, or even do imm math using
them.  We can also avoid re-flushing an imm.
 2013-11-10 15:50:14 -08:00
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7f9cbc0f10 armjit: Minor cleanup and logging tweaks. 2013-11-10 15:12:40 -08:00
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455a7e090d Compile the cache instruction to nothing. 
Was showing up in a few profiles, does nothing currently.
 2013-11-10 14:38:10 -08:00
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1cc68f50ca armjit: Small optimization to syscall instr. 2013-11-10 14:38:10 -08:00
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b30928036e armjit: Avoid flushing an imm in beq/bne/etc. 
We might be able to STMIA it instead.
 2013-11-10 14:38:10 -08:00
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285ec1fad5 armjit: Implement mult/multu for immediates. 
Uncommon, but may reduce instructions a bit.
 2013-11-10 14:38:09 -08:00
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9bec82873c armjit: inline byteswaps of imm values. 2013-11-10 14:38:08 -08:00
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06c8cb9174 armjit: Do shifts with imms as much as possible. 
This may even make an imm operand2 safe that wasn't before.
 2013-11-10 14:38:08 -08:00
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b2c2a87511 Fix omitted CC_AL reset, fixes #4498. 
Was breaking non-fastmem lwl/lwr/etc.
 2013-11-10 09:24:40 -08:00
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b310edc5f8 Fix typo in ARM debug build. 2013-11-09 15:58:27 -08:00
Henrik Rydgard
d1c012d75e ARM: Open up all 32 accessible VFP registers if NEON is available. 2013-11-09 20:18:20 +01:00
Henrik Rydgard
0a844ce98d Delete functions for vsge and vslt, these have been rolled into VecDo3 2013-11-09 19:29:52 +01:00
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a3a061a69f armjit: Optimize a division by a power of two. 
These really happen.
 2013-11-09 08:43:53 -08:00
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1776c85882 armjit: Implement a software divide for divu. 
It's not actually that much code.
 2013-11-09 08:43:52 -08:00
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b2a240d105 armjit: Implement msub/msubu. 2013-11-09 08:43:52 -08:00
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3aa8706ae7 armjit: Optimize lwl/lwr against an imm address. 2013-11-09 08:43:48 -08:00
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4026944b02 armjit: Handle lwl/lwr (not pretty, though.) 2013-11-09 08:42:30 -08:00
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54168b173e armjit: Clean up some magic numbers. 2013-11-09 08:25:08 -08:00
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6038d96b46 armjit: Flush regs using STMIA where possible. 2013-11-09 08:25:07 -08:00
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e686ff59bf armjit: Allocate regs in preferred slots. 
This may allow better flushing.  Not sure if these are the best regs,
but if they aren't it shouldn't really hurt.
 2013-11-09 08:25:07 -08:00
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cb3bb73148 armjit: Improve GPR typesafety. 2013-11-09 08:24:15 -08:00
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945b8bf5c5 armjit: optimize reverse subtract, avoid temp imms. 
If we have a non-op2 imm, get rid of it asap.  If we have a op2 friendly
imm, keep it.
 2013-11-09 08:18:43 -08:00