mirror of
https://github.com/libretro/ppsspp.git
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290 lines
7.4 KiB
C++
290 lines
7.4 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "../../Core.h"
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#include "../../CoreTiming.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSInt.h"
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#include "../MIPSTables.h"
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#include "ArmRegCache.h"
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#include "ArmJit.h"
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#include "../../../ext/disarm.h"
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void DisassembleArm(const u8 *data, int size) {
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char temp[256];
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for (int i = 0; i < size; i += 4) {
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const u32 *codePtr = (const u32 *)(data + i);
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u32 inst = codePtr[0];
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u32 next = (i < size - 4) ? codePtr[1] : 0;
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// MAGIC SPECIAL CASE for MOVW/MOVT readability!
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if ((inst & 0x0FF00000) == 0x03000000 && (next & 0x0FF00000) == 0x03400000) {
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u32 low = ((inst & 0x000F0000) >> 4) | (inst & 0x0FFF);
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u32 hi = ((next & 0x000F0000) >> 4) | (next & 0x0FFF);
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int reg0 = (inst & 0x0000F000) >> 12;
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int reg1 = (next & 0x0000F000) >> 12;
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if (reg0 == reg1) {
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sprintf(temp, "%08x MOV32? %s, %04x%04x", (u32)inst, ArmRegName(reg0), hi, low);
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INFO_LOG(DYNA_REC, "A: %s", temp);
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i += 4;
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continue;
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}
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}
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ArmDis((u32)codePtr, inst, temp);
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INFO_LOG(DYNA_REC, "A: %s", temp);
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}
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}
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namespace MIPSComp
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{
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Jit::Jit(MIPSState *mips) : blocks(mips), gpr(mips), mips_(mips)
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{
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blocks.Init();
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gpr.SetEmitter(this);
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//fpr.SetEmitter(this);
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AllocCodeSpace(1024 * 1024 * 16); // 32MB is the absolute max because that's what an ARM branch instruction can reach, backwards and forwards.
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GenerateFixedCode();
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}
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void Jit::FlushAll()
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{
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gpr.FlushAll();
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//fpr.Flush(FLUSH_ALL);
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}
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void Jit::ClearCache()
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{
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blocks.Clear();
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ClearCodeSpace();
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GenerateFixedCode();
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}
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void Jit::ClearCacheAt(u32 em_address)
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{
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// TODO: Properly.
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ClearCache();
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}
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void Jit::CompileAt(u32 addr)
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{
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u32 op = Memory::Read_Instruction(addr);
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MIPSCompileOp(op);
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}
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void Jit::Compile(u32 em_address)
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{
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if (GetSpaceLeft() < 0x10000 || blocks.IsFull())
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{
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ClearCache();
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}
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int block_num = blocks.AllocateBlock(em_address);
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ArmJitBlock *b = blocks.GetBlock(block_num);
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blocks.FinalizeBlock(block_num, jo.enableBlocklink, DoJit(em_address, b));
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}
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void Jit::RunLoopUntil(u64 globalticks)
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{
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// TODO: copy globalticks somewhere
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((void (*)())enterCode)();
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}
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const u8 *Jit::DoJit(u32 em_address, ArmJitBlock *b)
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{
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js.cancel = false;
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js.blockStart = js.compilerPC = mips_->pc;
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js.downcountAmount = 0;
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js.curBlock = b;
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js.compiling = true;
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js.inDelaySlot = false;
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// We add a check before the block, used when entering from a linked block.
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b->checkedEntry = GetCodePtr();
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// Downcount flag check. The last block decremented downcounter, and the flag should still be available.
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SetCC(CC_LT);
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ARMABI_MOVI2R(R0, js.blockStart);
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MovToPC(R0);
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B((const void *)outerLoop);
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SetCC(CC_AL);
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b->normalEntry = GetCodePtr();
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// TODO: this needs work
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MIPSAnalyst::AnalysisResults analysis; // = MIPSAnalyst::Analyze(em_address);
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gpr.Start(analysis);
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int numInstructions = 0;
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int cycles = 0;
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static int dontLogBlocks = 20;
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static int logBlocks = 40;
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if (logBlocks > 0) logBlocks--;
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if (dontLogBlocks > 0) dontLogBlocks--;
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#define LOGASM
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#ifdef LOGASM
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char temp[256];
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#endif
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while (js.compiling)
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{
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gpr.SetCompilerPC(js.compilerPC); // Let it know for log messages
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u32 inst = Memory::Read_Instruction(js.compilerPC);
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#ifdef LOGASM
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if (logBlocks > 0 && dontLogBlocks == 0) {
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MIPSDisAsm(inst, js.compilerPC, temp, true);
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INFO_LOG(DYNA_REC, "M: %08x %s", js.compilerPC, temp);
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}
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#endif
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js.downcountAmount += MIPSGetInstructionCycleEstimate(inst);
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MIPSCompileOp(inst);
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// FlushAll(); ///HACKK
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js.compilerPC += 4;
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numInstructions++;
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}
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#ifdef LOGASM
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if (logBlocks > 0 && dontLogBlocks == 0) {
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MIPSDisAsm(Memory::Read_Instruction(js.compilerPC), js.compilerPC, temp, true);
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INFO_LOG(DYNA_REC, "M: %08x %s", js.compilerPC, temp);
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}
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#endif
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b->codeSize = GetCodePtr() - b->normalEntry;
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#ifdef LOGASM
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if (logBlocks > 0 && dontLogBlocks == 0) {
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INFO_LOG(DYNA_REC, "=============== ARM ===============");
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DisassembleArm(b->normalEntry, GetCodePtr() - b->normalEntry);
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}
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#endif
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AlignCode16();
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// Don't forget to zap the instruction cache!
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FlushIcache();
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b->originalSize = numInstructions;
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return b->normalEntry;
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}
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void Jit::Comp_RunBlock(u32 op)
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{
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// This shouldn't be necessary, the dispatcher should catch us before we get here.
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ERROR_LOG(DYNA_REC, "Comp_RunBlock should never be reached!");
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}
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void Jit::Comp_Generic(u32 op)
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{
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FlushAll();
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MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
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if (func)
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{
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ARMABI_MOVI2R(R0, js.compilerPC);
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MovToPC(R0);
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ARMABI_MOVI2R(R0, op);
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QuickCallFunction(R1, (void *)func);
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}
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}
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void Jit::MovFromPC(ARMReg r) {
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LDR(r, R10, offsetof(MIPSState, pc));
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}
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void Jit::MovToPC(ARMReg r) {
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STR(R10, r, offsetof(MIPSState, pc));
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}
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void Jit::DoDownCount()
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{
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LDR(R1, R10, offsetof(MIPSState, downcount));
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Operand2 op2;
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if (TryMakeOperand2(js.downcountAmount, op2)) // We can enlarge this if we used rotations
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{
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SUBS(R1, R1, op2);
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STR(R10, R1, offsetof(MIPSState, downcount));
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} else {
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// Should be fine to use R2 here, flushed the regcache anyway.
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// If js.downcountAmount can be expressed as an Imm8, we don't need this anyway.
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ARMABI_MOVI2R(R2, js.downcountAmount);
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SUBS(R1, R1, R2);
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STR(R10, R1, offsetof(MIPSState, downcount));
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}
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}
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// IDEA - could have a WriteDualExit that takes two destinations and two condition flags,
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// and just have conditional that set PC "twice". This only works when we fall back to dispatcher
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// though, as we need to have the SUBS flag set in the end. So with block linking in the mix,
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// I don't think this gives us that much benefit.
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void Jit::WriteExit(u32 destination, int exit_num)
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{
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DoDownCount();
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//If nobody has taken care of this yet (this can be removed when all branches are done)
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ArmJitBlock *b = js.curBlock;
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b->exitAddress[exit_num] = destination;
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b->exitPtrs[exit_num] = GetWritableCodePtr();
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// Link opportunity!
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int block = blocks.GetBlockNumberFromStartAddress(destination);
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if (block >= 0 && jo.enableBlocklink) {
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// It exists! Joy of joy!
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B(blocks.GetBlock(block)->checkedEntry);
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b->linkStatus[exit_num] = true;
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} else {
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ARMABI_MOVI2R(R0, destination);
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MovToPC(R0);
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B((const void *)dispatcher);
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}
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}
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void Jit::WriteExitDestInR(ARMReg Reg)
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{
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MovToPC(Reg);
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DoDownCount();
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// TODO: shouldn't need an indirect branch here...
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B((const void *)dispatcher);
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}
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void Jit::WriteSyscallExit()
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{
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DoDownCount();
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B((const void *)dispatcherCheckCoreState);
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}
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6) & 0x1F)
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#define _POS ((op>>6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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//memory regions:
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//
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// 08-0A
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// 48-4A
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// 04-05
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// 44-45
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// mov eax, addrreg
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// shr eax, 28
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// mov eax, [table+eax]
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// mov dreg, [eax+offreg]
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}
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