mirror of
https://github.com/libretro/ppsspp.git
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246 lines
8.3 KiB
C++
246 lines
8.3 KiB
C++
#include "Common/ArmEmitter.h"
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#include "Core/MIPS/ARM/ArmRegCacheFPU.h"
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#include "Core/MIPS/ARM/ArmJit.h"
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#include "Core/MIPS/JitCommon/JitState.h"
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#include "Core/MIPS/MIPSVFPUUtils.h"
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#include "ext/disarm.h"
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#include "UnitTest.h"
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static bool CheckLast(ArmGen::ARMXEmitter &emit, const char *comp) {
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u32 instr;
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memcpy(&instr, emit.GetCodePtr() - 4, 4);
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char disasm[512];
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ArmDis(0, instr, disasm, sizeof(disasm), true);
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EXPECT_EQ_STR(std::string(disasm), std::string(comp));
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return true;
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}
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static void DisassembleARMBetween(const u8 *start, const u8 *end) {
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while (start < end) {
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char disasm[512];
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uint32_t instr;
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memcpy(&instr, start, 4);
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ArmDis(0, instr, disasm, sizeof(disasm), true);
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printf("%s\n", disasm);
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start += 4;
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}
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}
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bool TestArmEmitter() {
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using namespace ArmGen;
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u32 code[512];
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ARMXEmitter emitter((u8 *)code);
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emitter.VNEG(S1, S2);
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RET(CheckLast(emitter, "eef10a41 VNEG s1, s2"));
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emitter.LDR(R3, R7);
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RET(CheckLast(emitter, "e5973000 LDR r3, [r7, #0]"));
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emitter.VLDR(S3, R8, 48);
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RET(CheckLast(emitter, "edd81a0c VLDR s3, [r8, #48]"));
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emitter.VSTR(S5, R12, -36);
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RET(CheckLast(emitter, "ed4c2a09 VSTR s5, [r12, #-36]"));
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emitter.VADD(S1, S2, S3);
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RET(CheckLast(emitter, "ee710a21 VADD s1, s2, s3"));
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emitter.VADD(D1, D2, D3);
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RET(CheckLast(emitter, "ee321b03 VADD d1, d2, d3"));
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emitter.VSUB(S1, S2, S3);
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RET(CheckLast(emitter, "ee710a61 VSUB s1, s2, s3"));
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emitter.VMUL(S7, S8, S9);
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RET(CheckLast(emitter, "ee643a24 VMUL s7, s8, s9"));
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emitter.VMUL(S0, S5, S10);
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RET(CheckLast(emitter, "ee220a85 VMUL s0, s5, s10"));
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emitter.VNMUL(S7, S8, S9);
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RET(CheckLast(emitter, "ee643a64 VNMUL s7, s8, s9"));
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emitter.VMLA(S7, S8, S9);
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RET(CheckLast(emitter, "ee443a24 VMLA s7, s8, s9"));
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emitter.VNMLA(S7, S8, S9);
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RET(CheckLast(emitter, "ee543a64 VNMLA s7, s8, s9"));
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emitter.VNMLS(S7, S8, S9);
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RET(CheckLast(emitter, "ee543a24 VNMLS s7, s8, s9"));
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emitter.VABS(S1, S2);
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RET(CheckLast(emitter, "eef00ac1 VABS s1, s2"));
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emitter.VMOV(S1, S2);
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RET(CheckLast(emitter, "eef00a41 VMOV s1, s2"));
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emitter.VMOV(D1, D2);
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RET(CheckLast(emitter, "eeb01b42 VMOV d1, d2"));
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emitter.VCMP(S1, S2);
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RET(CheckLast(emitter, "eef40a41 VCMP s1, s2"));
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emitter.VCMPE(S1, S2);
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RET(CheckLast(emitter, "eef40ac1 VCMPE s1, s2"));
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emitter.VSQRT(S1, S2);
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RET(CheckLast(emitter, "eef10ac1 VSQRT s1, s2"));
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emitter.VDIV(S1, S2, S3);
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RET(CheckLast(emitter, "eec10a21 VDIV s1, s2, s3"));
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emitter.VMRS(R1);
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RET(CheckLast(emitter, "eef11a10 VMRS r1"));
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emitter.VMSR(R7);
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RET(CheckLast(emitter, "eee17a10 VMSR r7"));
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emitter.VMRS_APSR();
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RET(CheckLast(emitter, "eef1fa10 VMRS APSR"));
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emitter.VCVT(S0, S1, TO_INT | IS_SIGNED);
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RET(CheckLast(emitter, "eebd0a60 VCVT ..."));
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emitter.VMOV_imm(I_32, R0, VIMM___x___x, 0xF3);
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emitter.VMOV_imm(I_8, R0, VIMMxxxxxxxx, 0xF3);
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emitter.VMOV_immf(Q0, 1.0f);
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emitter.VMOV_immf(Q0, -1.0f);
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emitter.VBIC_imm(I_32, R0, VIMM___x___x, 0xF3);
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emitter.VMVN_imm(I_32, R0, VIMM___x___x, 0xF3);
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emitter.VPADD(F_32, D0, D0, D0);
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emitter.VMOV(Q14, Q2);
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emitter.VMOV(S3, S6);
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RET(CheckLast(emitter, "eef01a43 VMOV s3, s6"));
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emitter.VMOV_imm(I_32, R0, VIMM___x___x, 0xF3);
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emitter.VMOV_imm(I_8, R0, VIMMxxxxxxxx, 0xF3);
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emitter.VMOV_immf(Q0, 1.0f);
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RET(CheckLast(emitter, "f2870f50 VMOV q0, 1.0"));
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emitter.VMOV_immf(Q0, -1.0f);
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emitter.VBIC_imm(I_32, R0, VIMM___x___x, 0xF3);
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emitter.VMVN_imm(I_32, R0, VIMM___x___x, 0xF3);
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emitter.VPADD(F_32, D0, D0, D0);
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RET(CheckLast(emitter, "f3000d00 VPADD.f32 d0, d0, d0"));
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emitter.VMOV(Q14, Q2);
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emitter.VMLA_scalar(F_32, Q8, Q13, DScalar(D8, 1));
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RET(CheckLast(emitter, "f3ea01e8 VMLA.f32 q8, q13, d8[1]"));
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emitter.VMOV(S9, R3);
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RET(CheckLast(emitter, "ee043a90 VMOV s9, r3"));
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emitter.VMOV(R9, S3);
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RET(CheckLast(emitter, "ee119a90 VMOV r9, s3"));
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emitter.VMVN(Q1, Q13);
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RET(CheckLast(emitter, "f3b025ea VMVN q1, q13"));
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emitter.VMOV(S3, S6);
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RET(CheckLast(emitter, "eef01a43 VMOV s3, s6"));
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emitter.VMOV(S25, S21);
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RET(CheckLast(emitter, "eef0ca6a VMOV s25, s21"));
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emitter.VLD1(I_32, D19, R3, 2, ALIGN_NONE, R_PC);
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RET(CheckLast(emitter, "f4633a8f VLD1.32 {d19-d20}, [r3]"));
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emitter.VST1(I_32, D23, R9, 1, ALIGN_NONE, R_PC);
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RET(CheckLast(emitter, "f449778f VST1.32 {d23}, [r9]"));
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emitter.VLD1_lane(F_32, D8, R3, 0, ALIGN_NONE, R_PC);
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RET(CheckLast(emitter, "f4a3880f VLD1.32 {d8[0]}, [r3]"));
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emitter.VLD1_lane(I_8, D8, R3, 2, ALIGN_NONE, R_PC);
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RET(CheckLast(emitter, "f4a3804f VLD1.i8 {d8[2]}, [r3]"));
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emitter.VADD(I_8, D3, D4, D19);
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RET(CheckLast(emitter, "f2043823 VADD.i8 d3, d4, d19"));
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emitter.VADD(I_32, D3, D4, D19);
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RET(CheckLast(emitter, "f2243823 VADD.i32 d3, d4, d19"));
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emitter.VADD(F_32, D3, D4, D19);
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RET(CheckLast(emitter, "f2043d23 VADD.f32 d3, d4, d19"));
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emitter.VSUB(I_16, Q5, Q6, Q15);
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RET(CheckLast(emitter, "f31ca86e VSUB.i16 q5, q6, q15"));
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emitter.VMUL(F_32, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f3042d56 VMUL.f32 q1, q2, q3"));
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emitter.VMUL(F_32, Q13, Q15, Q14);
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RET(CheckLast(emitter, "f34eadfc VMUL.f32 q13, q15, q14"));
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emitter.VADD(F_32, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f2042d46 VADD.f32 q1, q2, q3"));
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emitter.VADD(F_32, Q11, Q11, Q10);
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RET(CheckLast(emitter, "f2466de4 VADD.f32 q11, q11, q10"));
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emitter.VMLA(F_32, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f2042d56 VMLA.f32 q1, q2, q3"));
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emitter.VMLS(F_32, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f2242d56 VMLS.f32 q1, q2, q3"));
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emitter.VMLS(I_16, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f3142946 VMLS.i16 q1, q2, q3"));
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emitter.VEOR(Q0, Q1, Q2);
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RET(CheckLast(emitter, "f3020154 VEOR q0, q1, q2"));
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emitter.VORR(Q1, Q2, Q3);
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RET(CheckLast(emitter, "f2242156 VORR q1, q2, q3"));
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emitter.VORR(D1, D2, D3);
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RET(CheckLast(emitter, "f2221113 VORR d1, d2, d3"));
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emitter.VAND(Q1, Q2, Q3);
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RET(CheckLast(emitter, "f2042156 VAND q1, q2, q3"));
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emitter.VDUP(F_32, Q14, D30, 1);
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RET(CheckLast(emitter, "f3fccc6e VDUP.32 q14, d30[1]"));
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// TODO: This is broken.
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// emitter.VDUP(F_32, D14, D30, 1);
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// RET(CheckLast(emitter, "f3bcec2e VDUP.32 d14, d30[1]"));
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//emitter.VNEG(S1, S2);
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//RET(CheckLast(emitter, "eef10a60 VNEG.f32 s1, s1"));
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emitter.VNEG(F_32, Q1, Q2);
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RET(CheckLast(emitter, "f3b927c4 VNEG.f32 q1, q2"));
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//emitter.VABS(F_32, Q1, Q2);
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//RET(CheckLast(emitter, "f3b92744 VABS.f32 q1, q2"));
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emitter.VMOV(D26, D30);
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RET(CheckLast(emitter, "eef0ab6e VMOV d26, d30"));
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emitter.VMUL_scalar(F_32, Q12, Q8, DScalar(D0, 0));
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RET(CheckLast(emitter, "f3e089c0 VMUL.f32 q12, q8, d0[0]"));
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emitter.VMUL_scalar(F_32, Q1, Q2, DScalar(D7, 0));
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RET(CheckLast(emitter, "f3a42947 VMUL.f32 q1, q2, d7[0]"));
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emitter.VMUL_scalar(F_32, D1, D2, QScalar(Q7, 0));
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RET(CheckLast(emitter, "f2a2194e VMUL.f32 d1, d2, d14[0]"));
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emitter.VMLA_scalar(F_32, Q1, Q2, DScalar(D7, 0));
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RET(CheckLast(emitter, "f3a42147 VMLA.f32 q1, q2, d7[0]"));
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emitter.VMIN(F_32, D3, D4, D19);
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RET(CheckLast(emitter, "f2243f23 VMIN.f32 d3, d4, d19"));
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emitter.VMAX(F_32, Q3, Q4, Q9);
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RET(CheckLast(emitter, "f2086f62 VMAX.f32 q3, q4, q9"));
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//emitter.VMOV(S1, 112);
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//RET(CheckLast(emitter, "eef70a00 VMOV.f32 s1, #112"));
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const u8 *codeStart = emitter.GetCodePtr();
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MIPSState mips;
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MIPSComp::JitState js;
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MIPSComp::ArmJitOptions jo;
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ArmRegCacheFPU fpr(&mips, &js, &jo);
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fpr.SetEmitter(&emitter);
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int C000 = GetColumnName(0, M_4x4, 0, 0);
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int C010 = GetColumnName(0, M_4x4, 1, 0);
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int C020 = GetColumnName(0, M_4x4, 2, 0);
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int C030 = GetColumnName(0, M_4x4, 3, 0);
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int R000 = GetRowName(0, M_4x4, 0, 0);
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int R001 = GetRowName(0, M_4x4, 1, 0);
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int R002 = GetRowName(0, M_4x4, 2, 0);
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int R003 = GetRowName(0, M_4x4, 3, 0);
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printf("Col 010: %s\n", GetVectorNotation(C010, V_Quad));
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printf("Row 003: %s\n", GetVectorNotation(R003, V_Quad));
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MIPSAnalyst::AnalysisResults results;
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memset(&results, 0, sizeof(results));
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using namespace ArmJitConstants;
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fpr.Start(results);
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fpr.QMapReg(C000, V_Quad, MAP_DIRTY);
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fpr.QMapReg(C010, V_Quad, MAP_DIRTY);
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fpr.QMapReg(C020, V_Quad, MAP_DIRTY);
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fpr.QMapReg(C030, V_Quad, MAP_DIRTY);
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emitter.ORR(R0, R0, R0);
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fpr.QMapReg(R000, V_Quad, MAP_DIRTY);
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fpr.FlushAll();
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fpr.Start(results);
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emitter.ORR(R0, R0, R0);
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fpr.QMapReg(R000, V_Quad, MAP_DIRTY);
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fpr.QMapReg(R001, V_Quad, MAP_DIRTY);
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fpr.QMapReg(R002, V_Quad, MAP_DIRTY);
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fpr.QMapReg(R003, V_Quad, MAP_DIRTY);
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emitter.ORR(R0, R0, R0);
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fpr.QMapReg(C000, V_Quad, MAP_DIRTY);
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fpr.FlushAll();
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const u8 *codeEnd = emitter.GetCodePtr();
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DisassembleARMBetween(codeStart, codeEnd);
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return true;
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}
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