mirror of
https://github.com/libretro/ppsspp.git
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258 lines
7.2 KiB
C++
258 lines
7.2 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Common/Log.h"
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#include "Common/x64Emitter.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/x86/RegCacheFPU.h"
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u32 FPURegCache::tempValues[NUM_TEMPS];
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FPURegCache::FPURegCache() : mips(0), emit(0) {
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memset(regs, 0, sizeof(regs));
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memset(xregs, 0, sizeof(xregs));
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vregs = regs + 32;
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}
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void FPURegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) {
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this->mips = mips;
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for (int i = 0; i < NUM_X_FPREGS; i++) {
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xregs[i].mipsReg = -1;
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xregs[i].dirty = false;
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}
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for (int i = 0; i < NUM_MIPS_FPRS; i++) {
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regs[i].location = GetDefaultLocation(i);
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regs[i].away = false;
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regs[i].locked = false;
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regs[i].tempLocked = false;
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}
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}
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void FPURegCache::SpillLock(int p1, int p2, int p3, int p4) {
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regs[p1].locked = true;
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if (p2 != 0xFF) regs[p2].locked = true;
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if (p3 != 0xFF) regs[p3].locked = true;
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if (p4 != 0xFF) regs[p4].locked = true;
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}
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void FPURegCache::SpillLockV(const u8 *v, VectorSize sz) {
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for (int i = 0; i < GetNumVectorElements(sz); i++) {
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vregs[v[i]].locked = true;
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}
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}
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void FPURegCache::SpillLockV(int vec, VectorSize sz) {
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u8 v[4];
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GetVectorRegs(v, sz, vec);
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SpillLockV(v, sz);
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}
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void FPURegCache::MapRegV(int vreg, int flags) {
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BindToRegister(vreg + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0);
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}
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void FPURegCache::MapRegsV(int vec, VectorSize sz, int flags) {
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u8 v[4];
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GetVectorRegs(v, sz, vec);
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SpillLockV(v, sz);
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for (int i = 0; i < GetNumVectorElements(sz); i++) {
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BindToRegister(v[i] + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0);
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}
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}
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void FPURegCache::MapRegsV(const u8 *v, VectorSize sz, int flags) {
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SpillLockV(v, sz);
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for (int i = 0; i < GetNumVectorElements(sz); i++) {
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BindToRegister(v[i] + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0);
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}
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}
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void FPURegCache::ReleaseSpillLock(int mipsreg)
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{
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regs[mipsreg].locked = false;
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}
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void FPURegCache::ReleaseSpillLocks() {
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for (int i = 0; i < NUM_MIPS_FPRS; i++)
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regs[i].locked = false;
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for (int i = TEMP0; i < TEMP0 + NUM_TEMPS; ++i)
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DiscardR(i);
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}
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void FPURegCache::BindToRegister(const int i, bool doLoad, bool makeDirty) {
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_assert_msg_(DYNA_REC, !regs[i].location.IsImm(), "WTF - load - imm");
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if (!regs[i].away) {
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// Reg is at home in the memory register file. Let's pull it out.
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X64Reg xr = GetFreeXReg();
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_assert_msg_(DYNA_REC, xr < NUM_X_FPREGS, "WTF - load - invalid reg");
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xregs[xr].mipsReg = i;
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xregs[xr].dirty = makeDirty;
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OpArg newloc = ::Gen::R(xr);
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if (doLoad) {
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if (!regs[i].location.IsImm() && (regs[i].location.offset & 0x3)) {
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PanicAlert("WARNING - misaligned fp register location %i", i);
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}
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emit->MOVSS(xr, regs[i].location);
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}
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regs[i].location = newloc;
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regs[i].away = true;
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} else {
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// There are no immediates in the FPR reg file, so we already had this in a register. Make dirty as necessary.
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xregs[RX(i)].dirty |= makeDirty;
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_assert_msg_(DYNA_REC, regs[i].location.IsSimpleReg(), "not loaded and not simple.");
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}
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}
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void FPURegCache::StoreFromRegister(int i) {
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_assert_msg_(DYNA_REC, !regs[i].location.IsImm(), "WTF - store - imm");
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if (regs[i].away) {
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X64Reg xr = regs[i].location.GetSimpleReg();
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_assert_msg_(DYNA_REC, xr < NUM_X_FPREGS, "WTF - store - invalid reg");
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xregs[xr].dirty = false;
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xregs[xr].mipsReg = -1;
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OpArg newLoc = GetDefaultLocation(i);
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emit->MOVSS(newLoc, xr);
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regs[i].location = newLoc;
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regs[i].away = false;
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} else {
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// _assert_msg_(DYNA_REC,0,"already stored");
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}
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}
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void FPURegCache::DiscardR(int i) {
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_assert_msg_(DYNA_REC, !regs[i].location.IsImm(), "FPU can't handle imm yet.");
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if (regs[i].away) {
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X64Reg xr = regs[i].location.GetSimpleReg();
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_assert_msg_(DYNA_REC, xr < NUM_X_FPREGS, "DiscardR: MipsReg had bad X64Reg");
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// Note that we DO NOT write it back here. That's the whole point of Discard.
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xregs[xr].dirty = false;
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xregs[xr].mipsReg = -1;
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regs[i].location = GetDefaultLocation(i);
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regs[i].away = false;
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regs[i].tempLocked = false;
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} else {
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// _assert_msg_(DYNA_REC,0,"already stored");
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regs[i].tempLocked = false;
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}
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}
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bool FPURegCache::IsTempX(X64Reg xr) {
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return xregs[xr].mipsReg >= TEMP0;
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}
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int FPURegCache::GetTempR() {
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for (int r = TEMP0; r < TEMP0 + NUM_TEMPS; ++r) {
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if (!regs[r].away && !regs[r].tempLocked) {
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regs[r].tempLocked = true;
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return r;
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}
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}
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_assert_msg_(DYNA_REC, 0, "Regcache ran out of temp regs, might need to DiscardR() some.");
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return -1;
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}
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void FPURegCache::Flush() {
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for (int i = 0; i < NUM_MIPS_FPRS; i++) {
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if (regs[i].locked) {
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PanicAlert("Somebody forgot to unlock MIPS reg %i.", i);
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}
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if (regs[i].away) {
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if (regs[i].location.IsSimpleReg()) {
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X64Reg xr = RX(i);
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StoreFromRegister(i);
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xregs[xr].dirty = false;
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} else if (regs[i].location.IsImm()) {
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StoreFromRegister(i);
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} else {
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_assert_msg_(DYNA_REC,0,"Jit64 - Flush unhandled case, reg %i PC: %08x", i, mips->pc);
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}
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}
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}
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}
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OpArg FPURegCache::GetDefaultLocation(int reg) const {
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if (reg < 32) {
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return M(&mips->f[reg]);
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} else if (reg < 32 + 128) {
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return M(&mips->v[reg - 32]);
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} else {
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return M(&tempValues[reg - 32 - 128]);
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}
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}
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int FPURegCache::SanityCheck() const {
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for (int i = 0; i < NUM_MIPS_FPRS; i++) {
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if (regs[i].away) {
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if (regs[i].location.IsSimpleReg()) {
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Gen::X64Reg simple = regs[i].location.GetSimpleReg();
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if (xregs[simple].mipsReg != i)
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return 2;
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}
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else if (regs[i].location.IsImm())
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return 3;
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}
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}
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return 0;
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}
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const int *FPURegCache::GetAllocationOrder(int &count) {
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static const int allocationOrder[] = {
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#ifdef _M_X64
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XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5
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#elif _M_IX86
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XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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#endif
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};
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count = sizeof(allocationOrder) / sizeof(int);
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return allocationOrder;
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}
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X64Reg FPURegCache::GetFreeXReg() {
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int aCount;
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const int *aOrder = GetAllocationOrder(aCount);
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for (int i = 0; i < aCount; i++) {
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X64Reg xr = (X64Reg)aOrder[i];
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if (xregs[xr].mipsReg == -1) {
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return (X64Reg)xr;
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}
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}
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//Okay, not found :( Force grab one
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//TODO - add a pass to grab xregs whose mipsreg is not used in the next 3 instructions
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for (int i = 0; i < aCount; i++) {
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X64Reg xr = (X64Reg)aOrder[i];
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int preg = xregs[xr].mipsReg;
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if (!regs[preg].locked) {
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StoreFromRegister(preg);
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return xr;
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}
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}
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//Still no dice? Die!
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_assert_msg_(DYNA_REC, 0, "Regcache ran out of regs");
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return (X64Reg) -1;
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}
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void FPURegCache::FlushX(X64Reg reg) {
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if (reg >= NUM_X_FPREGS)
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PanicAlert("Flushing non existent reg");
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if (xregs[reg].mipsReg != -1) {
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StoreFromRegister(xregs[reg].mipsReg);
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}
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}
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