mirror of
https://github.com/libretro/ppsspp.git
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434 lines
11 KiB
C++
434 lines
11 KiB
C++
#include "Common/ChunkFile.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/Reporting.h"
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#include "Core/HLE/HLE.h"
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#include "PpcRegCache.h"
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#include "ppcEmitter.h"
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#include "PpcJit.h"
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#include <ppcintrinsics.h>
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11 ) & 0x1F)
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#define LOOPOPTIMIZATION 0
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// We can disable nice delay slots.
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#define CONDITIONAL_NICE_DELAYSLOT delaySlotIsNice = false;
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// #define CONDITIONAL_NICE_DELAYSLOT ;
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#define SHOW_JS_COMPILER_PC { printf("js.compilerPC: %08x\n", js.compilerPC); }
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#define BRANCH_COMPILE_LOG { printf("JIT(%8x): %s => %d - %08x\n", (u32)GetCodePtr() ,__FUNCTION__, cc, js.compilerPC); }
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using namespace MIPSAnalyst;
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using namespace PpcGen;
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namespace MIPSComp
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{
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void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op&0xFFFF)<<2;
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int rt = _RT;
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int rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC+4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
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{
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gpr.MapReg(rs);
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CMPLI(gpr.R(rs), 0);
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}
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else if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0) // only these are easily 'flippable'
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{
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gpr.MapReg(rt);
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CMPLI(gpr.R(rt), 0);
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}
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else
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{
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gpr.MapInIn(rs, rt);
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CMPL(gpr.R(rs), gpr.R(rt));
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}
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PpcGen::FixupBranch ptr;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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else
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FlushAll();
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ptr = B_Cond(cc);
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}
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else
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{
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FlushAll();
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ptr = B_Cond(cc);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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INFO_LOG(CPU, "targetAddr: %08x,js.compilerPC: %08x offset: %08x, op: %08x\n", targetAddr, js.compilerPC, offset, op);
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// Take the branch
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC+8, 1);
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js.compiling = false;
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}
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void Jit::BranchRSZeroComp(u32 op, PpcGen::FixupBranchType cc, bool andLink, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op&0xFFFF)<<2;
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int rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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gpr.MapReg(rs);
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CMPI(gpr.R(rs), 0);
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PpcGen::FixupBranch ptr;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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else
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FlushAll();
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ptr = B_Cond(cc);
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}
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else
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{
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FlushAll();
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ptr = B_Cond(cc);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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if (andLink)
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{
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//Break();
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MOVI2R(SREG, js.compilerPC + 8);
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STW(SREG, CTXREG, MIPS_REG_RA * 4);
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}
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, 1);
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js.compiling = false;
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}
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void Jit::Comp_RelBranch(u32 op) {
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// The CC flags here should be opposite of the actual branch becuase they skip the branching action.
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switch (op>>26)
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{
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case 4: BranchRSRTComp(op, _BNE, false); break;//beq
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case 5: BranchRSRTComp(op, _BEQ, false); break;//bne
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case 6: BranchRSZeroComp(op, _BGT, false, false); break;//blez
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case 7: BranchRSZeroComp(op, _BLE, false, false); break;//bgtz
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case 20: BranchRSRTComp(op, _BNE, true); break;//beql
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case 21: BranchRSRTComp(op, _BEQ, true); break;//bnel
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case 22: BranchRSZeroComp(op, _BGT, false, true); break;//blezl
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case 23: BranchRSZeroComp(op, _BLE, false, true); break;//bgtzl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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js.compiling = false;
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}
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void Jit::Comp_RelBranchRI(u32 op) {
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switch ((op >> 16) & 0x1F)
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{
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case 0: BranchRSZeroComp(op, _BGE, false, false); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltz
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case 1: BranchRSZeroComp(op, _BLT, false, false); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgez
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case 2: BranchRSZeroComp(op, _BGE, false, true); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 8; break;//bltzl
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case 3: BranchRSZeroComp(op, _BLT, false, true); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 8; break;//bgezl
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case 16: BranchRSZeroComp(op, _BGE, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltzal
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case 17: BranchRSZeroComp(op, _BLT, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgezal
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case 18: BranchRSZeroComp(op, _BGE, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else SkipLikely(); break;//bltzall
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case 19: BranchRSZeroComp(op, _BLT, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else SkipLikely(); break;//bgezall
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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js.compiling = false;
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchFPFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op & 0xFFFF) << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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FlushAll();
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LWZ(SREG, CTXREG, offsetof(MIPSState, fpcond));
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// change CR0
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ANDI(SREG, SREG, 1);
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PpcGen::FixupBranch ptr;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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ptr = B_Cond(cc);
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}
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else
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{
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ptr = B_Cond(cc);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, 1);
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js.compiling = false;
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}
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void Jit::Comp_FPUBranch(u32 op) {
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switch((op >> 16) & 0x1f)
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{
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case 0: BranchFPFlag(op, _BNE, false); break; // bc1f
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case 1: BranchFPFlag(op, _BEQ, false); break; // bc1t
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case 2: BranchFPFlag(op, _BNE, true); break; // bc1fl
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case 3: BranchFPFlag(op, _BEQ, true); break; // bc1tl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
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break;
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}
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js.compiling = false;
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchVFPUFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op & 0xFFFF) << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceVFPU(op, delaySlotOp);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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FlushAll();
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int imm3 = (op >> 18) & 7;
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MOVI2R(SREG, (u32)&(mips_->vfpuCtrl[VFPU_CTRL_CC]));
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LWZ(SREG, SREG, 0);
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// change CR0
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ANDI(SREG, SREG, 1 << imm3);
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PpcGen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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ptr = B_Cond(cc);
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}
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else
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{
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ptr = B_Cond(cc);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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js.inDelaySlot = false;
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// Take the branch
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, 1);
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js.compiling = false;
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}
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void Jit::Comp_VBranch(u32 op) {
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switch ((op >> 16) & 3)
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{
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case 0: BranchVFPUFlag(op, _BNE, false); break; // bvf
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case 1: BranchVFPUFlag(op, _BEQ, false); break; // bvt
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case 2: BranchVFPUFlag(op, _BNE, true); break; // bvfl
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case 3: BranchVFPUFlag(op, _BEQ, true); break; // bvtl
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}
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js.compiling = false;
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}
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void Jit::Comp_Jump(u32 op) {
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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u32 off = ((op & 0x03FFFFFF) << 2);
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u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
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switch (op >> 26)
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{
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case 2: //j
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CompileDelaySlot(DELAYSLOT_NICE);
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FlushAll();
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WriteExit(targetAddr, 0);
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break;
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case 3: //jal
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//Break();
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gpr.MapReg(MIPS_REG_RA, MAP_NOINIT | MAP_DIRTY);
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MOVI2R(gpr.R(MIPS_REG_RA), js.compilerPC + 8);
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CompileDelaySlot(DELAYSLOT_NICE);
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FlushAll();
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WriteExit(targetAddr, 0);
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break;
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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js.compiling = false;
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}
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void Jit::Comp_JumpReg(u32 op) {
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int rs = _RS;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (IsSyscall(delaySlotOp)) {
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gpr.MapReg(rs);
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PPCReg mRs = gpr.R(rs);
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MR(FLAGREG, mRs);
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MovToPC(FLAGREG); // For syscall to be able to return.
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CompileDelaySlot(DELAYSLOT_FLUSH);
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return; // Syscall wrote exit code.
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} else if (delaySlotIsNice) {
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CompileDelaySlot(DELAYSLOT_NICE);
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gpr.MapReg(rs);
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PPCReg mRs = gpr.R(rs);
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MR(FLAGREG, mRs); // Save the destination address through the delay slot. Could use isNice to avoid when the jit is fully implemented
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FlushAll();
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} else {
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// Delay slot
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gpr.MapReg(rs);
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PPCReg mRs = gpr.R(rs);
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MR(FLAGREG, mRs); // Save the destination address through the delay slot. Could use isNice to avoid when the jit is fully implemented
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CompileDelaySlot(DELAYSLOT_NICE);
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FlushAll();
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}
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switch (op & 0x3f)
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{
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case 8: //jr
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break;
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case 9: //jalr
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// mips->reg = js.compilerPC + 8;
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//Break();
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MOVI2R(SREG, js.compilerPC + 8);
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STW(SREG, CTXREG, MIPS_REG_RA * 4);
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break;
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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WriteExitDestInR(FLAGREG);
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js.compiling = false;
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}
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void Jit::Comp_Syscall(u32 op) {
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FlushAll();
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// If we're in a delay slot, this is off by one.
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const int offset = js.inDelaySlot ? -1 : 0;
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WriteDownCount(offset);
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js.downcountAmount = -offset;
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// CallSyscall(op);
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MOVI2R(R3, op);
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SaveDowncount(DCNTREG);
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QuickCallFunction((void *)&CallSyscall);
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RestoreDowncount(DCNTREG);
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WriteSyscallExit();
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js.compiling = false;
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}
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void Jit::Comp_Break(u32 op) {
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Comp_Generic(op);
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WriteSyscallExit();
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js.compiling = false;
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}
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} |