mirror of
https://github.com/libretro/ppsspp.git
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346 lines
8.5 KiB
C++
346 lines
8.5 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/Config.h"
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#include "Common/Common.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/x86/Jit.h"
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#include "Core/MIPS/x86/RegCache.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { Comp_Generic(op); return; }
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namespace MIPSComp
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{
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void Jit::CompFPTriArith(MIPSOpcode op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters)
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{
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int ft = _FT;
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int fs = _FS;
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int fd = _FD;
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fpr.SpillLock(fd, fs, ft);
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if (fs == fd)
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{
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fpr.BindToRegister(fd, true, true);
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(this->*arith)(fpr.RX(fd), fpr.R(ft));
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}
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else if (ft == fd && !orderMatters)
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{
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fpr.BindToRegister(fd, true, true);
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(this->*arith)(fpr.RX(fd), fpr.R(fs));
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}
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else if (ft != fd && fs != fd && ft != fs) {
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fpr.BindToRegister(fd, false, true);
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MOVSS(fpr.RX(fd), fpr.R(fs));
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(this->*arith)(fpr.RX(fd), fpr.R(ft));
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}
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else {
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fpr.BindToRegister(fd, true, true);
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MOVSS(XMM0, fpr.R(fs));
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(this->*arith)(XMM0, fpr.R(ft));
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MOVSS(fpr.RX(fd), R(XMM0));
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}
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fpr.ReleaseSpillLocks();
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}
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void Jit::Comp_FPU3op(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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switch (op & 0x3f)
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{
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case 0: CompFPTriArith(op, &XEmitter::ADDSS, false); break; //F(fd) = F(fs) + F(ft); //add
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case 1: CompFPTriArith(op, &XEmitter::SUBSS, true); break; //F(fd) = F(fs) - F(ft); //sub
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case 2: CompFPTriArith(op, &XEmitter::MULSS, false); break; //F(fd) = F(fs) * F(ft); //mul
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case 3: CompFPTriArith(op, &XEmitter::DIVSS, true); break; //F(fd) = F(fs) / F(ft); //div
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile FPU3Op instruction that can't be interpreted");
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break;
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}
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}
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static u32 MEMORY_ALIGNED16(ssLoadStoreTemp);
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void Jit::Comp_FPULS(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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s32 offset = _IMM16;
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int ft = _FT;
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MIPSGPReg rs = _RS;
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switch(op >> 26)
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{
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case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
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{
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gpr.Lock(rs);
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fpr.SpillLock(ft);
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fpr.BindToRegister(ft, false, true);
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JitSafeMem safe(this, rs, offset);
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OpArg src;
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if (safe.PrepareRead(src, 4))
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MOVSS(fpr.RX(ft), src);
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if (safe.PrepareSlowRead((void *) &Memory::Read_U32))
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{
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MOV(32, M((void *)&ssLoadStoreTemp), R(EAX));
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MOVSS(fpr.RX(ft), M((void *)&ssLoadStoreTemp));
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}
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safe.Finish();
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gpr.UnlockAll();
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fpr.ReleaseSpillLocks();
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}
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break;
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case 57: //Memory::Write_U32(FI(ft), addr); break; //swc1
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{
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gpr.Lock(rs);
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fpr.SpillLock(ft);
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fpr.BindToRegister(ft, true, false);
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JitSafeMem safe(this, rs, offset);
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OpArg dest;
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if (safe.PrepareWrite(dest, 4))
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MOVSS(dest, fpr.RX(ft));
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if (safe.PrepareSlowWrite())
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{
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MOVSS(M((void *)&ssLoadStoreTemp), fpr.RX(ft));
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safe.DoSlowWrite((void *) &Memory::Write_U32, M((void *)&ssLoadStoreTemp));
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}
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safe.Finish();
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gpr.UnlockAll();
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fpr.ReleaseSpillLocks();
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}
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break;
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default:
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_dbg_assert_msg_(CPU,0,"Trying to interpret FPULS instruction that can't be interpreted");
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break;
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}
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}
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static const u64 MEMORY_ALIGNED16(ssOneBits[2]) = {0x0000000100000001ULL, 0x0000000100000001ULL};
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static const u64 MEMORY_ALIGNED16(ssSignBits2[2]) = {0x8000000080000000ULL, 0x8000000080000000ULL};
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static const u64 MEMORY_ALIGNED16(ssNoSignMask[2]) = {0x7FFFFFFF7FFFFFFFULL, 0x7FFFFFFF7FFFFFFFULL};
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static u32 ssCompareTemp;
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void Jit::CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN)
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{
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MOVSS(XMM0, fpr.R(lhs));
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CMPSS(XMM0, fpr.R(rhs), compare);
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MOVSS(M((void *) ¤tMIPS->fpcond), XMM0);
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// This means that NaN also means true, e.g. !<> or !>, etc.
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if (allowNaN)
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{
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MOVSS(XMM0, fpr.R(lhs));
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CMPUNORDSS(XMM0, fpr.R(rhs));
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MOVSS(M((void *) &ssCompareTemp), XMM0);
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MOV(32, R(EAX), M((void *) &ssCompareTemp));
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OR(32, M((void *) ¤tMIPS->fpcond), R(EAX));
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}
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}
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void Jit::Comp_FPUComp(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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int fs = _FS;
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int ft = _FT;
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switch (op & 0xf)
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{
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case 0: //f
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case 8: //sf
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MOV(32, M((void *) ¤tMIPS->fpcond), Imm32(0));
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break;
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case 1: //un
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case 9: //ngle
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CompFPComp(fs, ft, CMP_UNORD);
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break;
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case 2: //eq
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case 10: //seq
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CompFPComp(fs, ft, CMP_EQ);
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break;
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case 3: //ueq
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case 11: //ngl
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CompFPComp(fs, ft, CMP_EQ, true);
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break;
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case 4: //olt
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case 12: //lt
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CompFPComp(fs, ft, CMP_LT);
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break;
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case 5: //ult
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case 13: //nge
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CompFPComp(ft, fs, CMP_NLE);
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break;
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case 6: //ole
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case 14: //le
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CompFPComp(fs, ft, CMP_LE);
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break;
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case 7: //ule
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case 15: //ngt
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CompFPComp(ft, fs, CMP_NLT);
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break;
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default:
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DISABLE;
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}
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}
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void Jit::Comp_FPU2op(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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int fs = _FS;
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int fd = _FD;
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switch (op & 0x3f)
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{
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case 5: //F(fd) = fabsf(F(fs)); break; //abs
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fpr.SpillLock(fd, fs);
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fpr.BindToRegister(fd, fd == fs, true);
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MOVSS(fpr.RX(fd), fpr.R(fs));
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PAND(fpr.RX(fd), M((void *)ssNoSignMask));
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fpr.ReleaseSpillLocks();
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break;
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case 6: //F(fd) = F(fs); break; //mov
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if (fd != fs) {
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fpr.SpillLock(fd, fs);
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fpr.BindToRegister(fd, fd == fs, true);
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MOVSS(fpr.RX(fd), fpr.R(fs));
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fpr.ReleaseSpillLocks();
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}
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break;
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case 7: //F(fd) = -F(fs); break; //neg
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fpr.SpillLock(fd, fs);
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fpr.BindToRegister(fd, fd == fs, true);
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MOVSS(fpr.RX(fd), fpr.R(fs));
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PXOR(fpr.RX(fd), M((void *)ssSignBits2));
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fpr.ReleaseSpillLocks();
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break;
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case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
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fpr.SpillLock(fd, fs); // this probably works, just badly tested
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fpr.BindToRegister(fd, fd == fs, true);
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SQRTSS(fpr.RX(fd), fpr.R(fs));
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fpr.ReleaseSpillLocks();
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return;
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case 13: //FsI(fd) = F(fs)>=0 ? (int)floorf(F(fs)) : (int)ceilf(F(fs)); break;//trunc.w.s
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{
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fpr.SpillLock(fs, fd);
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fpr.StoreFromRegister(fd);
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CVTTSS2SI(EAX, fpr.R(fs));
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// Did we get an indefinite integer value?
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CMP(32, R(EAX), Imm32(0x80000000));
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FixupBranch skip = J_CC(CC_NE);
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MOVSS(XMM0, fpr.R(fs));
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XORPS(XMM1, R(XMM1));
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CMPSS(XMM0, R(XMM1), CMP_LT);
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// At this point, -inf = 0xffffffff, inf/nan = 0x00000000.
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// We want -inf to be 0x80000000 inf/nan to be 0x7fffffff, so we flip those bits.
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MOVD_xmm(R(EAX), XMM0);
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XOR(32, R(EAX), Imm32(0x7fffffff));
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SetJumpTarget(skip);
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MOV(32, fpr.R(fd), R(EAX));
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fpr.ReleaseSpillLocks();
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}
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break;
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case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
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fpr.StoreFromRegister(fs);
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CVTSI2SS(XMM0, fpr.R(fs));
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MOVSS(fpr.R(fd), XMM0);
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break;
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case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
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case 14: //FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
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case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
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case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
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default:
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Comp_Generic(op);
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return;
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}
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}
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void Jit::Comp_mxc1(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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int fs = _FS;
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MIPSGPReg rt = _RT;
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switch((op >> 21) & 0x1f)
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{
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case 0: // R(rt) = FI(fs); break; //mfc1
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if (rt != MIPS_REG_ZERO) {
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fpr.BindToRegister(fs, true, false); // TODO: Seems the V register becomes dirty here? It shouldn't.
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gpr.BindToRegister(rt, false, true);
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MOVD_xmm(gpr.R(rt), fpr.RX(fs));
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}
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break;
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case 2: // R(rt) = currentMIPS->ReadFCR(fs); break; //cfc1
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Comp_Generic(op);
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return;
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case 4: //FI(fs) = R(rt); break; //mtc1
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gpr.BindToRegister(rt, true, false);
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fpr.BindToRegister(fs, false, true); // TODO: Seems the V register becomes dirty here? It shouldn't.
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MOVD_xmm(fpr.RX(fs), gpr.R(rt));
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return;
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case 6: //currentMIPS->WriteFCR(fs, R(rt)); break; //ctc1
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Comp_Generic(op);
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return;
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}
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}
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} // namespace MIPSComp
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