mirror of
https://github.com/libretro/ppsspp.git
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798 lines
24 KiB
C++
798 lines
24 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// WARNING - THIS LIBRARY IS NOT THREAD SAFE!!!
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#ifndef _DOLPHIN_INTEL_CODEGEN_
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#define _DOLPHIN_INTEL_CODEGEN_
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#include "Common.h"
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#if !defined(_M_IX86) && !defined(_M_X64)
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#error "Don't build this on arm."
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#endif
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namespace Gen
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{
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enum X64Reg
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{
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EAX = 0, EBX = 3, ECX = 1, EDX = 2,
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ESI = 6, EDI = 7, EBP = 5, ESP = 4,
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RAX = 0, RBX = 3, RCX = 1, RDX = 2,
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RSI = 6, RDI = 7, RBP = 5, RSP = 4,
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R8 = 8, R9 = 9, R10 = 10,R11 = 11,
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R12 = 12,R13 = 13,R14 = 14,R15 = 15,
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AL = 0, BL = 3, CL = 1, DL = 2,
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SIL = 6, DIL = 7, BPL = 5, SPL = 4,
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AH = 0x104, BH = 0x107, CH = 0x105, DH = 0x106,
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AX = 0, BX = 3, CX = 1, DX = 2,
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SI = 6, DI = 7, BP = 5, SP = 4,
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XMM0=0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,
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INVALID_REG = 0xFFFFFFFF
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};
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enum CCFlags
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{
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CC_O = 0,
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CC_NO = 1,
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CC_B = 2, CC_C = 2, CC_NAE = 2,
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CC_NB = 3, CC_NC = 3, CC_AE = 3,
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CC_Z = 4, CC_E = 4,
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CC_NZ = 5, CC_NE = 5,
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CC_BE = 6, CC_NA = 6,
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CC_NBE = 7, CC_A = 7,
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CC_S = 8,
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CC_NS = 9,
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CC_P = 0xA, CC_PE = 0xA,
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CC_NP = 0xB, CC_PO = 0xB,
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CC_L = 0xC, CC_NGE = 0xC,
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CC_NL = 0xD, CC_GE = 0xD,
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CC_LE = 0xE, CC_NG = 0xE,
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CC_NLE = 0xF, CC_G = 0xF
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};
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enum
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{
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NUMGPRs = 16,
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NUMXMMs = 16,
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};
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enum
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{
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SCALE_NONE = 0,
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SCALE_1 = 1,
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SCALE_2 = 2,
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SCALE_4 = 4,
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SCALE_8 = 8,
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SCALE_ATREG = 16,
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//SCALE_NOBASE_1 is not supported and can be replaced with SCALE_ATREG
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SCALE_NOBASE_2 = 34,
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SCALE_NOBASE_4 = 36,
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SCALE_NOBASE_8 = 40,
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SCALE_RIP = 0xFF,
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SCALE_IMM8 = 0xF0,
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SCALE_IMM16 = 0xF1,
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SCALE_IMM32 = 0xF2,
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SCALE_IMM64 = 0xF3,
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};
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enum NormalOp {
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nrmADD,
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nrmADC,
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nrmSUB,
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nrmSBB,
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nrmAND,
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nrmOR ,
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nrmXOR,
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nrmMOV,
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nrmTEST,
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nrmCMP,
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nrmXCHG,
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};
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enum
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{
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CMP_EQ = 0,
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CMP_LT = 1,
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CMP_LE = 2,
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CMP_UNORD = 3,
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CMP_NEQ = 4,
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CMP_NLT = 5,
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CMP_NLE = 6,
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CMP_ORD = 7,
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};
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class XEmitter;
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struct OpArg
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{
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OpArg() {} // dummy op arg, used for storage
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OpArg(u64 _offset, int _scale, X64Reg rmReg = RAX, X64Reg scaledReg = RAX)
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{
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operandReg = 0;
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scale = (u8)_scale;
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offsetOrBaseReg = (u16)rmReg;
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indexReg = (u16)scaledReg;
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//if scale == 0 never mind offseting
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offset = _offset;
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}
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void WriteRex(XEmitter *emit, int opBits, int bits, int customOp = -1) const;
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void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=(X64Reg)0xFF, bool warn_64bit_offset = true) const;
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void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits);
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// This one is public - must be written to
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u64 offset; // use RIP-relative as much as possible - 64-bit immediates are not available.
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u16 operandReg;
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void WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &operand, int bits) const;
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bool IsImm() const {return scale == SCALE_IMM8 || scale == SCALE_IMM16 || scale == SCALE_IMM32 || scale == SCALE_IMM64;}
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bool IsSimpleReg() const {return scale == SCALE_NONE;}
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bool IsSimpleReg(X64Reg reg) const {
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return GetSimpleReg() == reg;
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}
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bool CanDoOpWith(const OpArg &other) const
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{
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if (IsSimpleReg()) return true;
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if (!IsSimpleReg() && !other.IsSimpleReg() && !other.IsImm()) return false;
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return true;
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}
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int GetImmBits() const
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{
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switch (scale)
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{
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case SCALE_IMM8: return 8;
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case SCALE_IMM16: return 16;
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case SCALE_IMM32: return 32;
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case SCALE_IMM64: return 64;
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default: return -1;
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}
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}
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X64Reg GetSimpleReg() const
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{
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if (scale == SCALE_NONE)
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return (X64Reg)offsetOrBaseReg;
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else
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return INVALID_REG;
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}
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u32 GetImmValue() const {
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return (u32)offset;
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}
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// For loops.
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void IncreaseOffset(int sz) {
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offset += sz;
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}
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private:
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u8 scale;
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u16 offsetOrBaseReg;
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u16 indexReg;
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};
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inline OpArg M(const void *ptr) {return OpArg((u64)ptr, (int)SCALE_RIP);}
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template <typename T>
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inline OpArg M(const T *ptr) {return OpArg((u64)(const void *)ptr, (int)SCALE_RIP);}
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inline OpArg R(X64Reg value) {return OpArg(0, SCALE_NONE, value);}
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inline OpArg MatR(X64Reg value) {return OpArg(0, SCALE_ATREG, value);}
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inline OpArg MDisp(X64Reg value, int offset) {
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return OpArg((u32)offset, SCALE_ATREG, value);
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}
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inline OpArg MComplex(X64Reg base, X64Reg scaled, int scale, int offset) {
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return OpArg(offset, scale, base, scaled);
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}
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inline OpArg MScaled(X64Reg scaled, int scale, int offset) {
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if (scale == SCALE_1)
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return OpArg(offset, SCALE_ATREG, scaled);
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else
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return OpArg(offset, scale | 0x20, RAX, scaled);
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}
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inline OpArg MRegSum(X64Reg base, X64Reg offset) {
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return MComplex(base, offset, 1, 0);
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}
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inline OpArg Imm8 (u8 imm) {return OpArg(imm, SCALE_IMM8);}
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inline OpArg Imm16(u16 imm) {return OpArg(imm, SCALE_IMM16);} //rarely used
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inline OpArg Imm32(u32 imm) {return OpArg(imm, SCALE_IMM32);}
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inline OpArg Imm64(u64 imm) {return OpArg(imm, SCALE_IMM64);}
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#ifdef _M_X64
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inline OpArg ImmPtr(void* imm) {return Imm64((u64)imm);}
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#else
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inline OpArg ImmPtr(void* imm) {return Imm32((u32)imm);}
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#endif
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inline u32 PtrOffset(void* ptr, void* base) {
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#ifdef _M_X64
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s64 distance = (s64)ptr-(s64)base;
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if (distance >= 0x80000000LL ||
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distance < -0x80000000LL) {
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_assert_msg_(JIT, 0, "pointer offset out of range");
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return 0;
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}
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return (u32)distance;
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#else
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return (u32)ptr-(u32)base;
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#endif
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}
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//usage: int a[]; ARRAY_OFFSET(a,10)
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#define ARRAY_OFFSET(array,index) ((u32)((u64)&(array)[index]-(u64)&(array)[0]))
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//usage: struct {int e;} s; STRUCT_OFFSET(s,e)
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#define STRUCT_OFFSET(str,elem) ((u32)((u64)&(str).elem-(u64)&(str)))
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struct FixupBranch
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{
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u8 *ptr;
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int type; //0 = 8bit 1 = 32bit
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};
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typedef const u8* JumpTarget;
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class XEmitter
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{
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friend struct OpArg; // for Write8 etc
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private:
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u8 *code;
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void Rex(int w, int r, int x, int b);
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void WriteSimple1Byte(int bits, u8 byte, X64Reg reg);
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void WriteSimple2Byte(int bits, u8 byte1, u8 byte2, X64Reg reg);
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void WriteMulDivType(int bits, OpArg src, int ext);
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void WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2);
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void WriteShift(int bits, OpArg dest, OpArg &shift, int ext);
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void WriteBitTest(int bits, OpArg &dest, OpArg &index, int ext);
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void WriteMXCSR(OpArg arg, int ext);
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void WriteSSEOp(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg &a1, const OpArg &a2);
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protected:
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inline void Write8(u8 value) {
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//if (value == 0xcc) {
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// value = 0xcc; // set breakpoint here to find where mysterious 0xcc are written
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//}
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*code++ = value;
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}
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inline void Write16(u16 value) {*(u16*)code = (value); code += 2;}
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inline void Write32(u32 value) {*(u32*)code = (value); code += 4;}
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inline void Write64(u64 value) {*(u64*)code = (value); code += 8;}
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public:
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XEmitter() { code = NULL; }
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XEmitter(u8 *code_ptr) { code = code_ptr; }
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virtual ~XEmitter() {}
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void WriteModRM(int mod, int rm, int reg);
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void WriteSIB(int scale, int index, int base);
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void SetCodePtr(u8 *ptr);
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void ReserveCodeSpace(int bytes);
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const u8 *AlignCode4();
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const u8 *AlignCode16();
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const u8 *AlignCodePage();
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const u8 *GetCodePtr() const;
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u8 *GetWritableCodePtr();
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// Looking for one of these? It's BANNED!! Some instructions are slow on modern CPU
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// INC, DEC, LOOP, LOOPNE, LOOPE, ENTER, LEAVE, XCHG, XLAT, REP MOVSB/MOVSD, REP SCASD + other string instr.,
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// INC and DEC are slow on Intel Core, but not on AMD. They create a
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// false flag dependency because they only update a subset of the flags.
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// XCHG is SLOW and should be avoided.
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// Debug breakpoint
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void INT3();
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// Do nothing
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void NOP(int count = 1); //nop padding - TODO: fast nop slides, for amd and intel (check their manuals)
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// Save energy in wait-loops on P4 only. Probably not too useful.
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void PAUSE();
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// Flag control
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void STC();
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void CLC();
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void CMC();
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// These two can not be executed in 64-bit mode on early Intel 64-bit CPU:s, only on Core2 and AMD!
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void LAHF(); // 3 cycle vector path
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void SAHF(); // direct path fast
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// Stack control
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void PUSH(X64Reg reg);
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void POP(X64Reg reg);
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void PUSH(int bits, const OpArg ®);
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void POP(int bits, const OpArg ®);
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void PUSHF();
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void POPF();
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// Flow control
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void RET();
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void RET_FAST();
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void UD2();
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FixupBranch J(bool force5bytes = false);
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void JMP(const u8 * addr, bool force5Bytes = false);
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void JMP(OpArg arg);
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void JMPptr(const OpArg &arg);
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void JMPself(); //infinite loop!
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#ifdef CALL
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#undef CALL
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#endif
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void CALL(const void *fnptr);
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void CALLptr(OpArg arg);
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FixupBranch J_CC(CCFlags conditionCode, bool force5bytes = false);
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//void J_CC(CCFlags conditionCode, JumpTarget target);
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void J_CC(CCFlags conditionCode, const u8 * addr, bool force5Bytes = false);
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void SetJumpTarget(const FixupBranch &branch);
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void SETcc(CCFlags flag, OpArg dest);
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// Note: CMOV brings small if any benefit on current cpus.
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void CMOVcc(int bits, X64Reg dest, OpArg src, CCFlags flag);
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// Fences
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void LFENCE();
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void MFENCE();
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void SFENCE();
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// Bit scan
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void BSF(int bits, X64Reg dest, OpArg src); //bottom bit to top bit
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void BSR(int bits, X64Reg dest, OpArg src); //top bit to bottom bit
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// Cache control
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enum PrefetchLevel
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{
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PF_NTA, //Non-temporal (data used once and only once)
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PF_T0, //All cache levels
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PF_T1, //Levels 2+ (aliased to T0 on AMD)
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PF_T2, //Levels 3+ (aliased to T0 on AMD)
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};
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void PREFETCH(PrefetchLevel level, OpArg arg);
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void MOVNTI(int bits, OpArg dest, X64Reg src);
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void MOVNTDQ(OpArg arg, X64Reg regOp);
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void MOVNTPS(OpArg arg, X64Reg regOp);
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void MOVNTPD(OpArg arg, X64Reg regOp);
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// Multiplication / division
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void MUL(int bits, OpArg src); //UNSIGNED
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void IMUL(int bits, OpArg src); //SIGNED
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void IMUL(int bits, X64Reg regOp, OpArg src);
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void IMUL(int bits, X64Reg regOp, OpArg src, OpArg imm);
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void DIV(int bits, OpArg src);
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void IDIV(int bits, OpArg src);
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// Shift
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void ROL(int bits, OpArg dest, OpArg shift);
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void ROR(int bits, OpArg dest, OpArg shift);
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void RCL(int bits, OpArg dest, OpArg shift);
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void RCR(int bits, OpArg dest, OpArg shift);
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void SHL(int bits, OpArg dest, OpArg shift);
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void SHR(int bits, OpArg dest, OpArg shift);
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void SAR(int bits, OpArg dest, OpArg shift);
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// Bit Test
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void BT(int bits, OpArg dest, OpArg index);
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void BTS(int bits, OpArg dest, OpArg index);
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void BTR(int bits, OpArg dest, OpArg index);
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void BTC(int bits, OpArg dest, OpArg index);
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// Double-Precision Shift
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void SHRD(int bits, OpArg dest, OpArg src, OpArg shift);
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void SHLD(int bits, OpArg dest, OpArg src, OpArg shift);
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// Extend EAX into EDX in various ways
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void CWD(int bits = 16);
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inline void CDQ() {CWD(32);}
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inline void CQO() {CWD(64);}
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void CBW(int bits = 8);
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inline void CWDE() {CBW(16);}
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inline void CDQE() {CBW(32);}
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// Load effective address
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void LEA(int bits, X64Reg dest, OpArg src);
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// Integer arithmetic
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void NEG (int bits, OpArg src);
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void ADD (int bits, const OpArg &a1, const OpArg &a2);
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void ADC (int bits, const OpArg &a1, const OpArg &a2);
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void SUB (int bits, const OpArg &a1, const OpArg &a2);
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void SBB (int bits, const OpArg &a1, const OpArg &a2);
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void AND (int bits, const OpArg &a1, const OpArg &a2);
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void CMP (int bits, const OpArg &a1, const OpArg &a2);
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// Bit operations
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void NOT (int bits, OpArg src);
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void OR (int bits, const OpArg &a1, const OpArg &a2);
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void XOR (int bits, const OpArg &a1, const OpArg &a2);
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void MOV (int bits, const OpArg &a1, const OpArg &a2);
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void TEST(int bits, const OpArg &a1, const OpArg &a2);
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// Are these useful at all? Consider removing.
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void XCHG(int bits, const OpArg &a1, const OpArg &a2);
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void XCHG_AHAL();
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// Byte swapping (32 and 64-bit only).
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void BSWAP(int bits, X64Reg reg);
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// Sign/zero extension
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void MOVSX(int dbits, int sbits, X64Reg dest, OpArg src); //automatically uses MOVSXD if necessary
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void MOVZX(int dbits, int sbits, X64Reg dest, OpArg src);
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// WARNING - These two take 11-13 cycles and are VectorPath! (AMD64)
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void STMXCSR(OpArg memloc);
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void LDMXCSR(OpArg memloc);
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// Prefixes
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void LOCK();
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void REP();
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void REPNE();
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void FWAIT();
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// SSE/SSE2: Floating point arithmetic
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void ADDSS(X64Reg regOp, OpArg arg);
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void ADDSD(X64Reg regOp, OpArg arg);
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void SUBSS(X64Reg regOp, OpArg arg);
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void SUBSD(X64Reg regOp, OpArg arg);
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void MULSS(X64Reg regOp, OpArg arg);
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void MULSD(X64Reg regOp, OpArg arg);
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void DIVSS(X64Reg regOp, OpArg arg);
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void DIVSD(X64Reg regOp, OpArg arg);
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void MINSS(X64Reg regOp, OpArg arg);
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void MINSD(X64Reg regOp, OpArg arg);
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void MAXSS(X64Reg regOp, OpArg arg);
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void MAXSD(X64Reg regOp, OpArg arg);
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void SQRTSS(X64Reg regOp, OpArg arg);
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void SQRTSD(X64Reg regOp, OpArg arg);
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void RSQRTSS(X64Reg regOp, OpArg arg);
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// SSE/SSE2: Floating point bitwise (yes)
|
|
void CMPSS(X64Reg regOp, OpArg arg, u8 compare);
|
|
void CMPSD(X64Reg regOp, OpArg arg, u8 compare);
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|
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inline void CMPEQSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_EQ); }
|
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inline void CMPLTSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_LT); }
|
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inline void CMPLESS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_LE); }
|
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inline void CMPUNORDSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_UNORD); }
|
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inline void CMPNEQSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_NEQ); }
|
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inline void CMPNLTSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_NLT); }
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inline void CMPORDSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_ORD); }
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// I don't think these exist
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/*
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void ANDSD(X64Reg regOp, OpArg arg);
|
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void ANDNSS(X64Reg regOp, OpArg arg);
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void ANDNSD(X64Reg regOp, OpArg arg);
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void ORSS(X64Reg regOp, OpArg arg);
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void ORSD(X64Reg regOp, OpArg arg);
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void XORSS(X64Reg regOp, OpArg arg);
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void XORSD(X64Reg regOp, OpArg arg);
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|
*/
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// SSE/SSE2: Floating point packed arithmetic (x4 for float, x2 for double)
|
|
void ADDPS(X64Reg regOp, OpArg arg);
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void ADDPD(X64Reg regOp, OpArg arg);
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void SUBPS(X64Reg regOp, OpArg arg);
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void SUBPD(X64Reg regOp, OpArg arg);
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void CMPPS(X64Reg regOp, OpArg arg, u8 compare);
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void CMPPD(X64Reg regOp, OpArg arg, u8 compare);
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void MULPS(X64Reg regOp, OpArg arg);
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void MULPD(X64Reg regOp, OpArg arg);
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void DIVPS(X64Reg regOp, OpArg arg);
|
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void DIVPD(X64Reg regOp, OpArg arg);
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void MINPS(X64Reg regOp, OpArg arg);
|
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void MINPD(X64Reg regOp, OpArg arg);
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void MAXPS(X64Reg regOp, OpArg arg);
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void MAXPD(X64Reg regOp, OpArg arg);
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void SQRTPS(X64Reg regOp, OpArg arg);
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void SQRTPD(X64Reg regOp, OpArg arg);
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void RSQRTPS(X64Reg regOp, OpArg arg);
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|
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// SSE/SSE2: Floating point packed bitwise (x4 for float, x2 for double)
|
|
void ANDPS(X64Reg regOp, OpArg arg);
|
|
void ANDPD(X64Reg regOp, OpArg arg);
|
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void ANDNPS(X64Reg regOp, OpArg arg);
|
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void ANDNPD(X64Reg regOp, OpArg arg);
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void ORPS(X64Reg regOp, OpArg arg);
|
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void ORPD(X64Reg regOp, OpArg arg);
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void XORPS(X64Reg regOp, OpArg arg);
|
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void XORPD(X64Reg regOp, OpArg arg);
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// SSE/SSE2: Shuffle components. These are tricky - see Intel documentation.
|
|
void SHUFPS(X64Reg regOp, OpArg arg, u8 shuffle);
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void SHUFPD(X64Reg regOp, OpArg arg, u8 shuffle);
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// SSE/SSE2: Useful alternative to shuffle in some cases.
|
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void MOVDDUP(X64Reg regOp, OpArg arg);
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// THESE TWO ARE NEW AND UNTESTED
|
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void UNPCKLPS(X64Reg dest, OpArg src);
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void UNPCKHPS(X64Reg dest, OpArg src);
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// These are OK.
|
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void UNPCKLPD(X64Reg dest, OpArg src);
|
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void UNPCKHPD(X64Reg dest, OpArg src);
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|
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// SSE/SSE2: Compares.
|
|
void COMISS(X64Reg regOp, OpArg arg);
|
|
void COMISD(X64Reg regOp, OpArg arg);
|
|
void UCOMISS(X64Reg regOp, OpArg arg);
|
|
void UCOMISD(X64Reg regOp, OpArg arg);
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|
|
// SSE/SSE2: Moves. Use the right data type for your data to avoid slight penalties on some CPUs.
|
|
|
|
// Singles
|
|
void MOVAPS(X64Reg regOp, OpArg arg);
|
|
void MOVAPS(OpArg arg, X64Reg regOp);
|
|
void MOVUPS(X64Reg regOp, OpArg arg);
|
|
void MOVUPS(OpArg arg, X64Reg regOp);
|
|
// Doubles
|
|
void MOVAPD(X64Reg regOp, OpArg arg);
|
|
void MOVAPD(OpArg arg, X64Reg regOp);
|
|
void MOVUPD(X64Reg regOp, OpArg arg);
|
|
void MOVUPD(OpArg arg, X64Reg regOp);
|
|
// Integers (NOTE: untested - I added these then it turned out I didn't have a use for them after all).
|
|
void MOVDQA(X64Reg regOp, OpArg arg);
|
|
void MOVDQA(OpArg arg, X64Reg regOp);
|
|
void MOVDQU(X64Reg regOp, OpArg arg);
|
|
void MOVDQU(OpArg arg, X64Reg regOp);
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|
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void MOVSS(X64Reg regOp, OpArg arg);
|
|
void MOVSD(X64Reg regOp, OpArg arg);
|
|
void MOVSS(OpArg arg, X64Reg regOp);
|
|
void MOVSD(OpArg arg, X64Reg regOp);
|
|
|
|
void MOVD_xmm(X64Reg dest, const OpArg &arg);
|
|
void MOVQ_xmm(X64Reg dest, OpArg arg);
|
|
void MOVD_xmm(const OpArg &arg, X64Reg src);
|
|
void MOVQ_xmm(OpArg arg, X64Reg src);
|
|
|
|
// SSE/SSE2: Generates a mask from the high bits of the components of the packed register in question.
|
|
void MOVMSKPS(X64Reg dest, OpArg arg);
|
|
void MOVMSKPD(X64Reg dest, OpArg arg);
|
|
|
|
// SSE2: Selective byte store, mask in src register. EDI/RDI specifies store address. This is a weird one.
|
|
void MASKMOVDQU(X64Reg dest, X64Reg src);
|
|
void LDDQU(X64Reg dest, OpArg src);
|
|
|
|
// SSE/SSE2: Data type conversions.
|
|
void CVTPS2PD(X64Reg dest, OpArg src);
|
|
void CVTPD2PS(X64Reg dest, OpArg src);
|
|
void CVTSS2SD(X64Reg dest, OpArg src);
|
|
void CVTSD2SS(X64Reg dest, OpArg src);
|
|
void CVTSD2SI(X64Reg dest, OpArg src);
|
|
void CVTDQ2PD(X64Reg regOp, OpArg arg);
|
|
void CVTPD2DQ(X64Reg regOp, OpArg arg);
|
|
void CVTDQ2PS(X64Reg regOp, OpArg arg);
|
|
void CVTPS2DQ(X64Reg regOp, OpArg arg);
|
|
|
|
void CVTSI2SS(X64Reg xregdest, OpArg arg); // Yeah, destination really is a GPR like EAX!
|
|
void CVTSS2SI(X64Reg xregdest, OpArg arg); // Yeah, destination really is a GPR like EAX!
|
|
void CVTTSS2SI(X64Reg xregdest, OpArg arg); // Yeah, destination really is a GPR like EAX!
|
|
void CVTTSD2SI(X64Reg xregdest, OpArg arg); // Yeah, destination really is a GPR like EAX!
|
|
void CVTTPS2DQ(X64Reg regOp, OpArg arg);
|
|
|
|
// SSE2: Packed integer instructions
|
|
void PACKSSDW(X64Reg dest, OpArg arg);
|
|
void PACKSSWB(X64Reg dest, OpArg arg);
|
|
//void PACKUSDW(X64Reg dest, OpArg arg);
|
|
void PACKUSWB(X64Reg dest, OpArg arg);
|
|
|
|
void PUNPCKLBW(X64Reg dest, const OpArg &arg);
|
|
void PUNPCKLWD(X64Reg dest, const OpArg &arg);
|
|
void PUNPCKLDQ(X64Reg dest, const OpArg &arg);
|
|
|
|
void PAND(X64Reg dest, OpArg arg);
|
|
void PANDN(X64Reg dest, OpArg arg);
|
|
void PXOR(X64Reg dest, OpArg arg);
|
|
void POR(X64Reg dest, OpArg arg);
|
|
|
|
void PADDB(X64Reg dest, OpArg arg);
|
|
void PADDW(X64Reg dest, OpArg arg);
|
|
void PADDD(X64Reg dest, OpArg arg);
|
|
void PADDQ(X64Reg dest, OpArg arg);
|
|
|
|
void PADDSB(X64Reg dest, OpArg arg);
|
|
void PADDSW(X64Reg dest, OpArg arg);
|
|
void PADDUSB(X64Reg dest, OpArg arg);
|
|
void PADDUSW(X64Reg dest, OpArg arg);
|
|
|
|
void PSUBB(X64Reg dest, OpArg arg);
|
|
void PSUBW(X64Reg dest, OpArg arg);
|
|
void PSUBD(X64Reg dest, OpArg arg);
|
|
void PSUBQ(X64Reg dest, OpArg arg);
|
|
|
|
void PSUBSB(X64Reg dest, OpArg arg);
|
|
void PSUBSW(X64Reg dest, OpArg arg);
|
|
void PSUBUSB(X64Reg dest, OpArg arg);
|
|
void PSUBUSW(X64Reg dest, OpArg arg);
|
|
|
|
void PAVGB(X64Reg dest, OpArg arg);
|
|
void PAVGW(X64Reg dest, OpArg arg);
|
|
|
|
void PCMPEQB(X64Reg dest, OpArg arg);
|
|
void PCMPEQW(X64Reg dest, OpArg arg);
|
|
void PCMPEQD(X64Reg dest, OpArg arg);
|
|
|
|
void PCMPGTB(X64Reg dest, OpArg arg);
|
|
void PCMPGTW(X64Reg dest, OpArg arg);
|
|
void PCMPGTD(X64Reg dest, OpArg arg);
|
|
|
|
void PEXTRW(X64Reg dest, OpArg arg, u8 subreg);
|
|
void PINSRW(X64Reg dest, OpArg arg, u8 subreg);
|
|
|
|
void PMADDWD(X64Reg dest, OpArg arg);
|
|
void PSADBW(X64Reg dest, OpArg arg);
|
|
|
|
void PMAXSW(X64Reg dest, OpArg arg);
|
|
void PMAXUB(X64Reg dest, OpArg arg);
|
|
void PMINSW(X64Reg dest, OpArg arg);
|
|
void PMINUB(X64Reg dest, OpArg arg);
|
|
// SSE4 has PMAXSB and PMINSB and PMAXUW and PMINUW too if we need them.
|
|
|
|
void PMOVMSKB(X64Reg dest, OpArg arg);
|
|
void PSHUFB(X64Reg dest, OpArg arg);
|
|
|
|
void PSHUFLW(X64Reg dest, OpArg arg, u8 shuffle);
|
|
|
|
void PSRLW(X64Reg reg, int shift);
|
|
void PSRLD(X64Reg reg, int shift);
|
|
void PSRLQ(X64Reg reg, int shift);
|
|
|
|
void PSLLW(X64Reg reg, int shift);
|
|
void PSLLD(X64Reg reg, int shift);
|
|
void PSLLQ(X64Reg reg, int shift);
|
|
|
|
void PSRLDQ(X64Reg reg, int shift);
|
|
void PSLLDQ(X64Reg reg, int shift);
|
|
|
|
void PSRAW(X64Reg reg, int shift);
|
|
void PSRAD(X64Reg reg, int shift);
|
|
|
|
void RTDSC();
|
|
|
|
// Utility functions
|
|
// The difference between this and CALL is that this aligns the stack
|
|
// where appropriate.
|
|
void ABI_CallFunction(const void *func);
|
|
|
|
template <typename T>
|
|
void ABI_CallFunction(T (*func)()) {
|
|
ABI_CallFunction((const void *)func);
|
|
}
|
|
|
|
void ABI_CallFunction(const u8 *func) {
|
|
ABI_CallFunction((const void *)func);
|
|
}
|
|
|
|
void ABI_CallFunctionC16(const void *func, u16 param1);
|
|
void ABI_CallFunctionCC16(const void *func, u32 param1, u16 param2);
|
|
|
|
// These only support u32 parameters, but that's enough for a lot of uses.
|
|
// These will destroy the 1 or 2 first "parameter regs".
|
|
void ABI_CallFunctionC(const void *func, u32 param1);
|
|
void ABI_CallFunctionCC(const void *func, u32 param1, u32 param2);
|
|
void ABI_CallFunctionCCC(const void *func, u32 param1, u32 param2, u32 param3);
|
|
void ABI_CallFunctionCCP(const void *func, u32 param1, u32 param2, void *param3);
|
|
void ABI_CallFunctionCCCP(const void *func, u32 param1, u32 param2, u32 param3, void *param4);
|
|
void ABI_CallFunctionP(const void *func, void *param1);
|
|
void ABI_CallFunctionPPC(const void *func, void *param1, void *param2, u32 param3);
|
|
void ABI_CallFunctionAC(const void *func, const Gen::OpArg &arg1, u32 param2);
|
|
void ABI_CallFunctionACC(const void *func, const Gen::OpArg &arg1, u32 param2, u32 param3);
|
|
void ABI_CallFunctionA(const void *func, const Gen::OpArg &arg1);
|
|
void ABI_CallFunctionAA(const void *func, const Gen::OpArg &arg1, const Gen::OpArg &arg2);
|
|
|
|
// Pass a register as a parameter.
|
|
void ABI_CallFunctionR(const void *func, Gen::X64Reg reg1);
|
|
void ABI_CallFunctionRR(const void *func, Gen::X64Reg reg1, Gen::X64Reg reg2);
|
|
|
|
template <typename Tr, typename T1>
|
|
void ABI_CallFunctionC(Tr (*func)(T1), u32 param1) {
|
|
ABI_CallFunctionC((const void *)func, param1);
|
|
}
|
|
|
|
// A function that doesn't have any control over what it will do to regs,
|
|
// such as the dispatcher, should be surrounded by these.
|
|
void ABI_PushAllCalleeSavedRegsAndAdjustStack();
|
|
void ABI_PopAllCalleeSavedRegsAndAdjustStack();
|
|
|
|
// A function that doesn't know anything about it's surroundings, should
|
|
// be surrounded by these to establish a safe environment, where it can roam free.
|
|
// An example is a backpatch injected function.
|
|
void ABI_PushAllCallerSavedRegsAndAdjustStack();
|
|
void ABI_PopAllCallerSavedRegsAndAdjustStack();
|
|
|
|
unsigned int ABI_GetAlignedFrameSize(unsigned int frameSize);
|
|
void ABI_AlignStack(unsigned int frameSize);
|
|
void ABI_RestoreStack(unsigned int frameSize);
|
|
|
|
// Sets up a __cdecl function.
|
|
// Only x64 really needs the parameter count.
|
|
void ABI_EmitPrologue(int maxCallParams);
|
|
void ABI_EmitEpilogue(int maxCallParams);
|
|
|
|
#ifdef _M_IX86
|
|
inline int ABI_GetNumXMMRegs() { return 8; }
|
|
#else
|
|
inline int ABI_GetNumXMMRegs() { return 16; }
|
|
#endif
|
|
}; // class XEmitter
|
|
|
|
|
|
// Everything that needs to generate X86 code should inherit from this.
|
|
// You get memory management for free, plus, you can use all the MOV etc functions without
|
|
// having to prefix them with gen-> or something similar.
|
|
class XCodeBlock : public XEmitter
|
|
{
|
|
protected:
|
|
u8 *region;
|
|
size_t region_size;
|
|
|
|
public:
|
|
XCodeBlock() : region(NULL), region_size(0) {}
|
|
virtual ~XCodeBlock() { if (region) FreeCodeSpace(); }
|
|
|
|
// Call this before you generate any code.
|
|
void AllocCodeSpace(int size);
|
|
|
|
// Always clear code space with breakpoints, so that if someone accidentally executes
|
|
// uninitialized, it just breaks into the debugger.
|
|
void ClearCodeSpace();
|
|
|
|
// Call this when shutting down. Don't rely on the destructor, even though it'll do the job.
|
|
void FreeCodeSpace();
|
|
|
|
bool IsInSpace(const u8 *ptr) const
|
|
{
|
|
return ptr >= region && ptr < region + region_size;
|
|
}
|
|
|
|
// Cannot currently be undone. Will write protect the entire code region.
|
|
// Start over if you need to change the code (call FreeCodeSpace(), AllocCodeSpace()).
|
|
void WriteProtect();
|
|
|
|
void ResetCodePtr()
|
|
{
|
|
SetCodePtr(region);
|
|
}
|
|
|
|
size_t GetSpaceLeft() const
|
|
{
|
|
return region_size - (GetCodePtr() - region);
|
|
}
|
|
|
|
u8 *GetBasePtr() {
|
|
return region;
|
|
}
|
|
|
|
size_t GetOffset(const u8 *ptr) const {
|
|
return ptr - region;
|
|
}
|
|
};
|
|
|
|
} // namespace
|
|
|
|
#endif // _DOLPHIN_INTEL_CODEGEN_
|