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143 lines
3.5 KiB
C++
143 lines
3.5 KiB
C++
#include "Common/ChunkFile.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "PpcRegCache.h"
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#include "ppcEmitter.h"
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#include "PpcJit.h"
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11 ) & 0x1F)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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//#define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { Comp_Generic(op); return; }
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using namespace PpcGen;
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namespace MIPSComp
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{
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void Jit::SetRegToEffectiveAddress(PpcGen::PPCReg r, int rs, s16 offset) {
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if (offset) {
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ADDI(SREG, gpr.R(rs), offset);
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RLWINM(SREG, SREG, 0, 2, 31); // &= 0x3FFFFFFF
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} else {
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RLWINM(SREG, gpr.R(rs), 0, 2, 31); // &= 0x3FFFFFFF
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}
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}
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void Jit::Comp_ITypeMem(u32 op) {
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CONDITIONAL_DISABLE;
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int offset = (signed short)(op&0xFFFF);
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bool load = false;
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int rt = _RT;
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int rs = _RS;
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int o = op>>26;
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if (((op >> 29) & 1) == 0 && rt == 0) {
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// Don't load anything into $zr
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return;
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}
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u32 iaddr = gpr.IsImm(rs) ? offset + gpr.GetImm(rs) : 0xFFFFFFFF;
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bool doCheck = false;
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switch (o)
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{
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case 32: //lb
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case 33: //lh
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case 35: //lw
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case 36: //lbu
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case 37: //lhu
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load = true;
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case 40: //sb
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case 41: //sh
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case 43: //sw
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if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
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// We can compute the full address at compile time. Kickass.
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u32 addr = iaddr & 0x3FFFFFFF;
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// Must be OK even if rs == rt since we have the value from imm already.
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gpr.MapReg(rt, load ? MAP_NOINIT | MAP_DIRTY : 0);
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MOVI2R(SREG, addr);
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} else {
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_dbg_assert_msg_(JIT, !gpr.IsImm(rs), "Invalid immediate address? CPU bug?");
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load ? gpr.MapDirtyIn(rt, rs) : gpr.MapInIn(rt, rs);
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SetRegToEffectiveAddress(SREG, rs, offset);
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}
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switch (o)
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{
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// Load
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case 32: //lb
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LBZX(gpr.R(rt), BASEREG, SREG);
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EXTSB(gpr.R(rt), gpr.R(rt));
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break;
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case 33: //lh
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LHBRX(gpr.R(rt), BASEREG, SREG);
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EXTSH(gpr.R(rt), gpr.R(rt));
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break;
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case 35: //lw
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LWBRX(gpr.R(rt), BASEREG, SREG);
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break;
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case 36: //lbu
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LBZX (gpr.R(rt), BASEREG, SREG);
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break;
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case 37: //lhu
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LHBRX (gpr.R(rt), BASEREG, SREG);
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break;
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// Store
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case 40: //sb
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STBX (gpr.R(rt), BASEREG, SREG);
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break;
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case 41: //sh
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STHBRX(gpr.R(rt), BASEREG, SREG);
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break;
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case 43: //sw
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STWBRX(gpr.R(rt), BASEREG, SREG);
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break;
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}
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break;
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case 34: //lwl
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case 38: //lwr
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load = true;
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case 42: //swl
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case 46: //swr
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if (!js.inDelaySlot) {
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// Optimisation: Combine to single unaligned load/store
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bool isLeft = (o == 34 || o == 42);
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u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Find a matching shift in opposite direction with opposite offset.
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if (nextOp == (isLeft ? (op + (4<<26) - 3)
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: (op - (4<<26) + 3)))
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{
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EatInstruction(nextOp);
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nextOp = ((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x3FFFFFF); //lw, sw
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Comp_ITypeMem(nextOp);
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return;
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}
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}
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DISABLE; // Disabled until crashes are resolved.
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break;
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default:
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Comp_Generic(op);
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return ;
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}
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}
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}
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