mirror of
https://github.com/libretro/ppsspp.git
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304 lines
9.3 KiB
C++
304 lines
9.3 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "Globals.h"
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#include "Common/Thunk.h"
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#include "Asm.h"
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#if defined(ARM)
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#error DO NOT BUILD X86 JIT ON ARM
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#endif
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#include "Common/x64Emitter.h"
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#include "Core/MIPS/JitCommon/JitBlockCache.h"
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#include "Core/MIPS/JitCommon/JitState.h"
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#include "RegCache.h"
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#include "RegCacheFPU.h"
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namespace MIPSComp
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{
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// This is called when Jit hits a breakpoint. Returns 1 when hit.
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u32 JitBreakpoint();
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struct JitOptions
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{
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JitOptions();
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bool enableBlocklink;
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bool immBranches;
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bool continueBranches;
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bool continueJumps;
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int continueMaxInstructions;
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};
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// TODO: Hmm, humongous.
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struct RegCacheState {
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GPRRegCacheState gpr;
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FPURegCacheState fpr;
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};
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class Jit : public Gen::XCodeBlock
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{
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public:
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Jit(MIPSState *mips);
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virtual ~Jit();
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void DoState(PointerWrap &p);
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static void DoDummyState(PointerWrap &p);
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// Compiled ops should ignore delay slots
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// the compiler will take care of them by itself
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// OR NOT
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void Comp_Generic(MIPSOpcode op);
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void RunLoopUntil(u64 globalticks);
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void Compile(u32 em_address); // Compiles a block at current MIPS PC
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const u8 *DoJit(u32 em_address, JitBlock *b);
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bool IsInDispatch(const u8 *p) {
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return asm_.IsInSpace(p);
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}
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void Comp_RunBlock(MIPSOpcode op);
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void Comp_ReplacementFunc(MIPSOpcode op);
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// Ops
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void Comp_ITypeMem(MIPSOpcode op);
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void Comp_Cache(MIPSOpcode op);
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void Comp_RelBranch(MIPSOpcode op);
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void Comp_RelBranchRI(MIPSOpcode op);
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void Comp_FPUBranch(MIPSOpcode op);
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void Comp_FPULS(MIPSOpcode op);
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void Comp_FPUComp(MIPSOpcode op);
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void Comp_Jump(MIPSOpcode op);
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void Comp_JumpReg(MIPSOpcode op);
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void Comp_Syscall(MIPSOpcode op);
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void Comp_Break(MIPSOpcode op);
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void Comp_IType(MIPSOpcode op);
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void Comp_RType2(MIPSOpcode op);
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void Comp_RType3(MIPSOpcode op);
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void Comp_ShiftType(MIPSOpcode op);
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void Comp_Allegrex(MIPSOpcode op);
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void Comp_Allegrex2(MIPSOpcode op);
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void Comp_VBranch(MIPSOpcode op);
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void Comp_MulDivType(MIPSOpcode op);
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void Comp_Special3(MIPSOpcode op);
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void Comp_FPU3op(MIPSOpcode op);
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void Comp_FPU2op(MIPSOpcode op);
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void Comp_mxc1(MIPSOpcode op);
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void Comp_SV(MIPSOpcode op);
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void Comp_SVQ(MIPSOpcode op);
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void Comp_VPFX(MIPSOpcode op);
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void Comp_VVectorInit(MIPSOpcode op);
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void Comp_VMatrixInit(MIPSOpcode op);
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void Comp_VDot(MIPSOpcode op);
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void Comp_VecDo3(MIPSOpcode op);
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void Comp_VV2Op(MIPSOpcode op);
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void Comp_Mftv(MIPSOpcode op);
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void Comp_Vmtvc(MIPSOpcode op);
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void Comp_Vmmov(MIPSOpcode op);
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void Comp_VScl(MIPSOpcode op);
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void Comp_Vmmul(MIPSOpcode op);
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void Comp_Vmscl(MIPSOpcode op);
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void Comp_Vtfm(MIPSOpcode op);
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void Comp_VHdp(MIPSOpcode op);
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void Comp_VCrs(MIPSOpcode op);
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void Comp_VDet(MIPSOpcode op);
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void Comp_Vi2x(MIPSOpcode op);
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void Comp_Vx2i(MIPSOpcode op);
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void Comp_Vf2i(MIPSOpcode op);
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void Comp_Vi2f(MIPSOpcode op);
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void Comp_Vh2f(MIPSOpcode op);
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void Comp_Vcst(MIPSOpcode op);
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void Comp_Vhoriz(MIPSOpcode op);
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void Comp_VRot(MIPSOpcode op);
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void Comp_VIdt(MIPSOpcode op);
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void Comp_Vcmp(MIPSOpcode op);
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void Comp_Vcmov(MIPSOpcode op);
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void Comp_Viim(MIPSOpcode op);
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void Comp_Vfim(MIPSOpcode op);
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void Comp_VCrossQuat(MIPSOpcode op);
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void Comp_Vsgn(MIPSOpcode op);
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void Comp_Vocp(MIPSOpcode op);
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void Comp_DoNothing(MIPSOpcode op);
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int Replace_fabsf();
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void ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz);
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void ApplyPrefixD(const u8 *vregs, VectorSize sz);
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void GetVectorRegsPrefixS(u8 *regs, VectorSize sz, int vectorReg) {
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_assert_(js.prefixSFlag & JitState::PREFIX_KNOWN);
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GetVectorRegs(regs, sz, vectorReg);
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ApplyPrefixST(regs, js.prefixS, sz);
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}
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void GetVectorRegsPrefixT(u8 *regs, VectorSize sz, int vectorReg) {
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_assert_(js.prefixTFlag & JitState::PREFIX_KNOWN);
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GetVectorRegs(regs, sz, vectorReg);
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ApplyPrefixST(regs, js.prefixT, sz);
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}
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void GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg);
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void EatPrefix() { js.EatPrefix(); }
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JitBlockCache *GetBlockCache() { return &blocks; }
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AsmRoutineManager &Asm() { return asm_; }
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void ClearCache();
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void ClearCacheAt(u32 em_address, int length = 4);
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private:
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void GetStateAndFlushAll(RegCacheState &state);
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void RestoreState(const RegCacheState state);
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void FlushAll();
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void FlushPrefixV();
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void WriteDowncount(int offset = 0);
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// See CompileDelaySlotFlags for flags.
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void CompileDelaySlot(int flags, RegCacheState *state = NULL);
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void CompileDelaySlot(int flags, RegCacheState &state) {
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CompileDelaySlot(flags, &state);
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}
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void EatInstruction(MIPSOpcode op);
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void WriteExit(u32 destination, int exit_num);
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void WriteExitDestInReg(X64Reg reg);
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void WriteExitDestInEAX() { WriteExitDestInReg(EAX); }
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// void WriteRfiExitDestInEAX();
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void WriteSyscallExit();
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bool CheckJitBreakpoint(u32 addr, int downcountOffset);
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// Utility compilation functions
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void BranchFPFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely);
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void BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely);
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void BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool likely);
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void BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely);
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void BranchLog(MIPSOpcode op);
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void BranchLogExit(MIPSOpcode op, u32 dest, bool useEAX);
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// Utilities to reduce duplicated code
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void CompImmLogic(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &));
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void CompTriArith(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &), u32 (*doImm)(const u32, const u32));
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void CompShiftImm(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32));
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void CompShiftVar(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32));
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void CompITypeMemRead(MIPSOpcode op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc);
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void CompITypeMemWrite(MIPSOpcode op, u32 bits, void *safeFunc);
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void CompITypeMemUnpairedLR(MIPSOpcode op, bool isStore);
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void CompITypeMemUnpairedLRInner(MIPSOpcode op, X64Reg shiftReg);
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void CompBranchExits(CCFlags cc, u32 targetAddr, u32 notTakenAddr, bool delaySlotIsNice, bool likely, bool andLink);
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void CompFPTriArith(MIPSOpcode op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters);
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void CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN = false);
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void CallProtectedFunction(void *func, const OpArg &arg1);
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void CallProtectedFunction(void *func, const OpArg &arg1, const OpArg &arg2);
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void CallProtectedFunction(void *func, const u32 arg1, const u32 arg2, const u32 arg3);
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void CallProtectedFunction(void *func, const OpArg &arg1, const u32 arg2, const u32 arg3);
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bool PredictTakeBranch(u32 targetAddr, bool likely);
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bool CanContinueBranch() {
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if (!jo.continueBranches || js.numInstructions >= jo.continueMaxInstructions) {
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return false;
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}
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// Need at least 2 exits left over.
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if (js.nextExit >= MAX_JIT_BLOCK_EXITS - 2) {
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return false;
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}
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return true;
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}
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JitBlockCache blocks;
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JitOptions jo;
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JitState js;
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GPRRegCache gpr;
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FPURegCache fpr;
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AsmRoutineManager asm_;
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ThunkManager thunks;
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MIPSState *mips_;
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class JitSafeMem {
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public:
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JitSafeMem(Jit *jit, MIPSGPReg raddr, s32 offset, u32 alignMask = 0xFFFFFFFF);
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// Emit code necessary for a memory write, returns true if MOV to dest is needed.
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bool PrepareWrite(OpArg &dest, int size);
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// Emit code proceeding a slow write call, returns true if slow write is needed.
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bool PrepareSlowWrite();
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// Emit a slow write from src.
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void DoSlowWrite(void *safeFunc, const OpArg src, int suboffset = 0);
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// Emit code necessary for a memory read, returns true if MOV from src is needed.
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bool PrepareRead(OpArg &src, int size);
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// Emit code for a slow read call, and returns true if result is in EAX.
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bool PrepareSlowRead(void *safeFunc);
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// Cleans up final code for the memory access.
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void Finish();
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// Use this before anything else if you're gonna use the below.
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void SetFar();
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// WARNING: Only works for non-GPR. Do not use for reads into GPR.
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OpArg NextFastAddress(int suboffset);
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// WARNING: Only works for non-GPR. Do not use for reads into GPR.
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void NextSlowRead(void *safeFunc, int suboffset);
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private:
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enum ReadType {
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MEM_READ,
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MEM_WRITE,
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};
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OpArg PrepareMemoryOpArg(ReadType type);
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void PrepareSlowAccess();
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void MemCheckImm(ReadType type);
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void MemCheckAsm(ReadType type);
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bool ImmValid();
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Jit *jit_;
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MIPSGPReg raddr_;
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s32 offset_;
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int size_;
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bool needsCheck_;
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bool needsSkip_;
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bool far_;
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bool fast_;
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u32 alignMask_;
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u32 iaddr_;
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X64Reg xaddr_;
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FixupBranch tooLow_, tooHigh_, skip_;
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std::vector<FixupBranch> skipChecks_;
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const u8 *safe_;
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};
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friend class JitSafeMem;
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};
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typedef void (Jit::*MIPSCompileFunc)(MIPSOpcode opcode);
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typedef int (Jit::*MIPSReplaceFunc)();
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} // namespace MIPSComp
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