mirror of
https://github.com/libretro/ppsspp.git
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389 lines
11 KiB
C++
389 lines
11 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "base/logging.h"
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#include "Common/ArmEmitter.h"
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#include "Common/CPUDetect.h"
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#include "Core/MIPS/ARM/ArmRegCacheFPU.h"
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using namespace ArmGen;
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ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mips) : mips_(mips), vr(mr + 32) {
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}
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void ArmRegCacheFPU::Init(ARMXEmitter *emitter) {
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emit_ = emitter;
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}
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void ArmRegCacheFPU::Start(MIPSAnalyst::AnalysisResults &stats) {
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for (int i = 0; i < NUM_ARMFPUREG; i++) {
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ar[i].mipsReg = -1;
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ar[i].isDirty = false;
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}
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for (int i = 0; i < NUM_MIPSFPUREG; i++) {
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mr[i].loc = ML_MEM;
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mr[i].reg = INVALID_REG;
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mr[i].spillLock = false;
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mr[i].tempLock = false;
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}
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}
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static const ARMReg *GetMIPSAllocationOrder(int &count) {
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// We reserve S0-S1 as scratch. Can afford two registers. Maybe even four, which could simplify some things.
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static const ARMReg allocationOrder[] = {
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S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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};
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// With NEON, we have many more.
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static const ARMReg allocationOrderNEON[] = {
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S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15,
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S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31
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};
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// Disabled the NEON path due to issues so we limit ourselves to 16.
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if (false && cpu_info.bNEON) {
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count = sizeof(allocationOrderNEON) / sizeof(const int);
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return allocationOrderNEON;
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} else {
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count = sizeof(allocationOrder) / sizeof(const int);
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return allocationOrder;
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}
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}
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ARMReg ArmRegCacheFPU::MapReg(MIPSReg mipsReg, int mapFlags) {
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// Let's see if it's already mapped. If so we just need to update the dirty flag.
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// We don't need to check for ML_NOINIT because we assume that anyone who maps
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// with that flag immediately writes a "known" value to the register.
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if (mr[mipsReg].loc == ML_ARMREG) {
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if (ar[mr[mipsReg].reg].mipsReg != mipsReg) {
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ERROR_LOG(HLE, "Register mapping out of sync! %i", mipsReg);
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}
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if (mapFlags & MAP_DIRTY) {
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ar[mr[mipsReg].reg].isDirty = true;
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}
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//INFO_LOG(HLE, "Already mapped %i to %i", mipsReg, mr[mipsReg].reg);
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return (ARMReg)(mr[mipsReg].reg + S0);
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}
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// Okay, not mapped, so we need to allocate an ARM register.
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int allocCount;
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const ARMReg *allocOrder = GetMIPSAllocationOrder(allocCount);
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allocate:
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for (int i = 0; i < allocCount; i++) {
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int reg = allocOrder[i] - S0;
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if (ar[reg].mipsReg == -1) {
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// That means it's free. Grab it, and load the value into it (if requested).
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ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
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if (!(mapFlags & MAP_NOINIT)) {
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if (mr[mipsReg].loc == ML_MEM && mipsReg < TEMP0) {
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emit_->VLDR((ARMReg)(reg + S0), CTXREG, GetMipsRegOffset(mipsReg));
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}
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}
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ar[reg].mipsReg = mipsReg;
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mr[mipsReg].loc = ML_ARMREG;
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mr[mipsReg].reg = reg;
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//INFO_LOG(HLE, "Mapped %i to %i", mipsReg, mr[mipsReg].reg);
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return (ARMReg)(reg + S0);
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}
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}
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// Still nothing. Let's spill a reg and goto 10.
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// TODO: Use age or something to choose which register to spill?
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// TODO: Spill dirty regs first? or opposite?
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int bestToSpill = -1;
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for (int i = 0; i < allocCount; i++) {
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int reg = allocOrder[i] - S0;
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if (ar[reg].mipsReg != -1 && (mr[ar[reg].mipsReg].spillLock || mr[ar[reg].mipsReg].tempLock))
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continue;
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bestToSpill = reg;
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break;
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}
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if (bestToSpill != -1) {
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FlushArmReg((ARMReg)(S0 + bestToSpill));
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goto allocate;
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}
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// Uh oh, we have all them spilllocked....
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ERROR_LOG(JIT, "Out of spillable registers at PC %08x!!!", mips_->pc);
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return INVALID_REG;
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}
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void ArmRegCacheFPU::MapInIn(MIPSReg rd, MIPSReg rs) {
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SpillLock(rd, rs);
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MapReg(rd);
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MapReg(rs);
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ReleaseSpillLock(rd);
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ReleaseSpillLock(rs);
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}
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void ArmRegCacheFPU::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) {
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SpillLock(rd, rs);
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bool overlap = avoidLoad && rd == rs;
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MapReg(rd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT));
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MapReg(rs);
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ReleaseSpillLock(rd);
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ReleaseSpillLock(rs);
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}
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void ArmRegCacheFPU::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad) {
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SpillLock(rd, rs, rt);
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bool overlap = avoidLoad && (rd == rs || rd == rt);
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MapReg(rd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT));
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MapReg(rt);
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MapReg(rs);
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ReleaseSpillLock(rd);
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ReleaseSpillLock(rs);
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ReleaseSpillLock(rt);
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}
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void ArmRegCacheFPU::SpillLockV(const u8 *v, VectorSize sz) {
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for (int i = 0; i < GetNumVectorElements(sz); i++) {
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vr[v[i]].spillLock = true;
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}
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}
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void ArmRegCacheFPU::SpillLockV(int vec, VectorSize sz) {
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u8 v[4];
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GetVectorRegs(v, sz, vec);
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SpillLockV(v, sz);
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}
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void ArmRegCacheFPU::MapRegV(int vreg, int flags) {
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MapReg(vreg + 32, flags);
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}
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void ArmRegCacheFPU::LoadToRegV(ARMReg armReg, int vreg) {
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if (vr[vreg].loc == ML_ARMREG) {
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emit_->VMOV(armReg, (ARMReg)(S0 + vr[vreg].reg));
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} else {
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MapRegV(vreg);
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emit_->VMOV(armReg, V(vreg));
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}
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}
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void ArmRegCacheFPU::MapRegsAndSpillLockV(int vec, VectorSize sz, int flags) {
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u8 v[4];
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GetVectorRegs(v, sz, vec);
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SpillLockV(v, sz);
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for (int i = 0; i < GetNumVectorElements(sz); i++) {
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MapRegV(v[i], flags);
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}
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}
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void ArmRegCacheFPU::MapRegsAndSpillLockV(const u8 *v, VectorSize sz, int flags) {
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SpillLockV(v, sz);
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for (int i = 0; i < GetNumVectorElements(sz); i++) {
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MapRegV(v[i], flags);
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}
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}
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void ArmRegCacheFPU::MapInInV(int vs, int vt) {
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SpillLockV(vs);
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SpillLockV(vt);
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MapRegV(vs);
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MapRegV(vt);
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ReleaseSpillLockV(vs);
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ReleaseSpillLockV(vt);
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}
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void ArmRegCacheFPU::MapDirtyInV(int vd, int vs, bool avoidLoad) {
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bool overlap = avoidLoad && (vd == vs);
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SpillLockV(vd);
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SpillLockV(vs);
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MapRegV(vd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT));
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MapRegV(vs);
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ReleaseSpillLockV(vd);
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ReleaseSpillLockV(vs);
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}
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void ArmRegCacheFPU::MapDirtyInInV(int vd, int vs, int vt, bool avoidLoad) {
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bool overlap = avoidLoad && ((vd == vs) || (vd == vt));
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SpillLockV(vd);
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SpillLockV(vs);
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SpillLockV(vt);
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MapRegV(vd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT));
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MapRegV(vs);
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MapRegV(vt);
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ReleaseSpillLockV(vd);
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ReleaseSpillLockV(vs);
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ReleaseSpillLockV(vt);
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}
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void ArmRegCacheFPU::FlushArmReg(ARMReg r) {
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int reg = r - S0;
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if (ar[reg].mipsReg == -1) {
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// Nothing to do, reg not mapped.
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return;
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}
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if (ar[reg].mipsReg != -1) {
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if (ar[reg].isDirty && mr[ar[reg].mipsReg].loc == ML_ARMREG)
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{
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//INFO_LOG(HLE, "Flushing ARM reg %i", reg);
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emit_->VSTR(r, CTXREG, GetMipsRegOffset(ar[reg].mipsReg));
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}
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// IMMs won't be in an ARM reg.
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mr[ar[reg].mipsReg].loc = ML_MEM;
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mr[ar[reg].mipsReg].reg = INVALID_REG;
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} else {
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ERROR_LOG(HLE, "Dirty but no mipsreg?");
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}
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ar[reg].isDirty = false;
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ar[reg].mipsReg = -1;
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}
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void ArmRegCacheFPU::FlushR(MIPSReg r) {
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switch (mr[r].loc) {
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case ML_IMM:
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// IMM is always "dirty".
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// IMM is not allowed for FP (yet).
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ERROR_LOG(HLE, "Imm in FP register?");
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break;
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case ML_ARMREG:
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if (mr[r].reg == (int)INVALID_REG) {
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ERROR_LOG(HLE, "FlushR: MipsReg had bad ArmReg");
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}
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if (ar[mr[r].reg].isDirty) {
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//INFO_LOG(HLE, "Flushing dirty reg %i", mr[r].reg);
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emit_->VSTR((ARMReg)(mr[r].reg + S0), CTXREG, GetMipsRegOffset(r));
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ar[mr[r].reg].isDirty = false;
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}
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ar[mr[r].reg].mipsReg = -1;
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break;
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case ML_MEM:
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// Already there, nothing to do.
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break;
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default:
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//BAD
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break;
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}
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mr[r].loc = ML_MEM;
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mr[r].reg = (int)INVALID_REG;
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}
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void ArmRegCacheFPU::DiscardR(MIPSReg r) {
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switch (mr[r].loc) {
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case ML_IMM:
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// IMM is always "dirty".
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// IMM is not allowed for FP (yet).
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ERROR_LOG(HLE, "Imm in FP register?");
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break;
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case ML_ARMREG:
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if (mr[r].reg == (int)INVALID_REG) {
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ERROR_LOG(HLE, "DiscardR: MipsReg had bad ArmReg");
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}
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// Note that we DO NOT write it back here. That's the whole point of Discard.
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ar[mr[r].reg].isDirty = false;
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ar[mr[r].reg].mipsReg = -1;
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break;
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case ML_MEM:
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// Already there, nothing to do.
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break;
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default:
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//BAD
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break;
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}
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mr[r].loc = ML_MEM;
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mr[r].reg = (int)INVALID_REG;
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mr[r].tempLock = false;
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mr[r].spillLock = false;
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}
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bool ArmRegCacheFPU::IsTempX(ARMReg r) const {
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return ar[r - S0].mipsReg >= TEMP0;
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}
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int ArmRegCacheFPU::GetTempR() {
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for (int r = TEMP0; r < TEMP0 + NUM_TEMPS; ++r) {
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if (mr[r].loc == ML_MEM && !mr[r].tempLock) {
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mr[r].tempLock = true;
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return r;
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}
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}
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ERROR_LOG(CPU, "Out of temp regs! Might need to DiscardR() some");
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_assert_msg_(DYNA_REC, 0, "Regcache ran out of temp regs, might need to DiscardR() some.");
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return -1;
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}
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void ArmRegCacheFPU::FlushAll() {
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// Discard temps!
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for (int i = TEMP0; i < TEMP0 + NUM_TEMPS; i++) {
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DiscardR(i);
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}
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for (int i = 0; i < NUM_MIPSFPUREG; i++) {
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FlushR(i);
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}
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// Sanity check
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for (int i = 0; i < NUM_ARMFPUREG; i++) {
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if (ar[i].mipsReg != -1) {
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ERROR_LOG(JIT, "Flush fail: ar[%i].mipsReg=%i", i, ar[i].mipsReg);
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}
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}
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}
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int ArmRegCacheFPU::GetMipsRegOffset(MIPSReg r) {
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// These are offsets within the MIPSState structure. First there are the GPRS, then FPRS, then the "VFPURs", then the VFPU ctrls.
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if (r < 32 + 128 + NUM_TEMPS)
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return (r + 32) << 2;
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ERROR_LOG(JIT, "bad mips register %i, out of range", r);
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return 0; // or what?
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}
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void ArmRegCacheFPU::SpillLock(MIPSReg r1, MIPSReg r2, MIPSReg r3, MIPSReg r4) {
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mr[r1].spillLock = true;
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if (r2 != -1) mr[r2].spillLock = true;
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if (r3 != -1) mr[r3].spillLock = true;
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if (r4 != -1) mr[r4].spillLock = true;
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}
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// This is actually pretty slow with all the 160 regs...
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void ArmRegCacheFPU::ReleaseSpillLocksAndDiscardTemps() {
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for (int i = 0; i < NUM_MIPSFPUREG; i++)
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mr[i].spillLock = false;
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for (int i = TEMP0; i < TEMP0 + NUM_TEMPS; ++i)
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DiscardR(i);
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}
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ARMReg ArmRegCacheFPU::R(int mipsReg) {
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if (mr[mipsReg].loc == ML_ARMREG) {
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return (ARMReg)(mr[mipsReg].reg + S0);
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} else {
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if (mipsReg < 32) {
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ERROR_LOG(JIT, "FReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg, compilerPC_, currentMIPS->DisasmAt(compilerPC_));
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} else if (mipsReg < 32 + 128) {
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ERROR_LOG(JIT, "VReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 32, compilerPC_, currentMIPS->DisasmAt(compilerPC_));
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} else {
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ERROR_LOG(JIT, "Tempreg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 128 - 32, compilerPC_, currentMIPS->DisasmAt(compilerPC_));
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}
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return INVALID_REG; // BAAAD
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}
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}
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